In computer science, a NOP, no-op, or NOOP (pronounced "no op"; short for no operation) is a machine language instruction and its assembly language mnemonic, programming language statement, or computer protocol command that does nothing.
Machine language instructions Some computer instruction sets include an instruction whose purpose is to not change the state of any of the programmer-accessible registers, status flags, or memory. It often takes a well-defined number of clock cycles to execute. In some instruction sets, there is no explicit NOP instruction; the assembly language mnemonic NOP represents a regular instruction with parameters that make it do nothing such as the SPARC's sethi 0, %g0.
A NOP must not access memory, as that could cause a memory fault or page fault.
A NOP is most commonly used for timing purposes, to force memory alignment, to prevent hazards, to occupy a branch delay slot, to render void an existing instruction such as a jump, as a target of an execute instruction, or as a place-holder to be replaced by active instructions later on in program development (or to replace removed instructions when reorganizing would be problematic or time-consuming). In some cases, a NOP can have minor side effects; for example, on the Motorola 68000 series of processors, the NOP opcode causes a synchronization of the pipeline.
Listed below are the NOP instruction for some CPU architectures:
CPU architecture Instruction mnemonic Bytes Opcode Notes Intel x86 CPU family NOP 1 0x90 0x90 is the one-byte encoding for XCHG AX,AX in 16-bit code and XCHG EAX,EAX in 32-bit code. In long mode, XCHG RAX,RAX requires two bytes, as it would begin with an REX.W prefix, making the encoding 0x48 0x90. However, 0x90 is interpreted as a NOP in long mode regardless of whether it is preceded by 0x48. multi-byte NOP 2–9 for Pentium Pro and later Intel processors, and all AMD AMD64 processors 0x66 0x90 0x0F 0x1F 0x00
0x0F 0x1F 0x40 0x00
0x0F 0x1F 0x44 0x00 0x00
0x66 0x0F 0x1F 0x44 0x00 0x00
0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 is the operand-size override prefix.
0x0F 0x1F is a two-byte NOP opcode that takes a ModR/M operand upon which no memory is accessed and no registers are written. ModR/M and operands added to this are:
0x00 is [EAX]
0x40 0x00 is [EAX + 00H]
0x44 0x00 0x00 is [EAX + EAX*1 + 00H]
0x80 0x00 0x00 0x00 0x00 is [EAX + 00000000H]
0x84 0x00 0x00 0x00 0x00 0x00 is [EAX + EAX*1 + 00000000H] FNOP 2 0xD9 0xD0 x87 floating-point coprocessor no-operation Intel 8008 LAA 1 0xC0 Load A from A Intel 8048 / MCS-48 family NOP 1 0x00 Intel 8051 / MCS-51 family NOP 1 0x00 Intel 8080, 8085, Zilog Z80 NOP 1 0x00 Intel i860 NOP 4 0xA0000000 Core no-operation. Opcode for an instruction to left-shift the all-0s register by itself. FNOP 4 0xB0000000 Floating-point no-operation. Opcode for , a shift-right-double instruction that takes the all-0s register as input and output. Intel i960 MOV g0,g0 4 0x5C801610 Move global register g0 to itself. Suggested opcode for cases where a no-op is needed. Intel IA-64 (Itanium) (qp) NOP.b imm21 41 bits 0x04000000000 On IA-64, the NOP instruction has five forms, each of which can be executed only on a particular execution unit type.
All five NOP forms include a 6-bit qp field (bits 5:0) and a 21-bit immediate field (bit 36 + bits 25:6). These fields may be set to any value with no effect on the operation of the instruction. (The encodings listed here result from setting these fields to all-0s – which is common but not required).
The NOP.x form of the instruction additionally consumes a second 41-bit instruction slot – the contents of this slot is considered to be providing 41 additional immediate-bits, for a total immediate-size of 62 bits. (qp) NOP.f imm21 41 bits 0x00008000000 (qp) NOP.i imm21 (qp) NOP.m imm21 41+41 bits 0x00008000000 imm41 32-bit ARM (A32) NOP 4 0x*320F000 Architectural ARM A32 NOP ("true" nop, with no register dependencies). Introduced with ARMv6K (ARM 1176, released in 2003), and present in all later ARM A32 processors. (The * indicates a 4-bit field that may take any value other than 0xF.) MOV r0,r0/NOP 4 0xE1A00000 Recommended A32 no-operation encoding for older 32-bit ARM processors that pre-date ARMv6K. Assemblers for A32 will usually output this opcode when given the "NOP" mnemonic unless they are told to target ARMv6K or later versions of the ARM architecture. ANDEQ r0,r0,r0 4 0x00000000 Bitwise-AND r0 with itself if equal. Commonly used no-op encoding due to the simplicity of its encoding. MOVNV r0,r0 4 0xF1A00000 Move r0 to itself never. Obsolete no-op encoding that used to be recommended for the ARM2/ARM3 processors in older Acorn Archimedes computers. Makes use of the NV ("never") condition code – which has been deprecated since 1993, with support fully removed with ARMv5. Thumb MOV r8,r8/NOP 2 0x46C0 Recommended Thumb no-operation encoding for older 32-bit Thumb processors that pre-date ARMv6T2. Assemblers for T32 will usually output this opcode when given the "NOP" mnemonic unless they are told to target ARMv6T2 or later versions of the ARM Thumb architecture. Thumb-2 (T32) NOP 2 0xBF00 Architectural ARM T32 (Thumb-2) NOPs ("true" nops, with no register dependencies). Introduced with ARMv6T2 (ARM 1156, released in 2003), and present in all later ARM T32 processors. NOP.W 4 0xF3AF8000 64-bit ARM (A64) NOP 4 0xD503201F Architectural NOP DEC Alpha NOP 4 0x47FF041F Integer NOP. Opcode for BIS r31,r31,r31, an instruction that bitwise-ORs the always-0 register with itself. FNOP 4 0x5FFF041F Floating-point NOP. Opcode for CPYS f31,f31,f31, an instruction that performs copy-sign with the always-0 register as source for both sign and exponent/mantissa, and stores the result in the always-0 register. UNOP 4 0x2FFE0000 Universal NOP. Opcode for LDQ_U r31,0($sp). The LDQ_U (unaligned load) opcode is, on 21164 and later, special-cased so that when used with the always-0 register as a destination register, no memory access is performed. The address register and displacement may take any value, but is most commonly given as 0($sp) which is stack pointer + zero. AMD 29k NOP 4 0x70400101 Opcode for aseq 0x40,gr1,gr1, an instruction that asserts that the stack register is equal to itself.AMD, AVR NOP 2 0x0000 one clock cycle COP400 NOP 1 0x44 COP8 NOP 1 0xB8 HP 3000 NOP 2 0x0000 HP 3000 stack operation instructions have most-significant four bits of 0 followed by two 6-bit stack opcodes, with stack NOP (0) used to pad when needed. 0x0000 would be NOP, NOP. Hyperstone E1 NOP 2 0x0300 Opcode for CHK L0,L0, a range-check instruction which produces an exception if the L0 register is greater than itself.Hyperstone Electronics GmbH, Hyperstone E1-32/E1-16 32-Bit-Microprocessor User's Manual, rev 03/96, pages 35,38,70. NOP 4 0x47000000 or 0x470nnnnn or 0x47n0nnnn where "n" is any 4-bit value. The NOP ("No-Op") and NOPR ("No-Op Register") are a subset of the "Branch on Condition" or "Branch on Condition Register" instructions, respectively; both versions have two options for generating a NO-OP.
In the case of both the NOP and NOPR instructions, the first 0 in the second byte is the "mask" value, the condition to test such as equal, not equal, high, low, etc. If the mask is 0, no branch occurs.
In the case of the NOPR instruction, the second value in the second byte is the register to branch on. If register 0 is chosen, no branch occurs regardless of the mask value. Thus, if either of the two values in the second byte is 0, the branch will not happen. If the first 0 in the second byte is 0, the value of the second value in the second byte is irrelevant on most processors; however, on the IBM System/360 Model 91, if that value refers to register 15, the instruction will wait for all previously-decoded instructions to complete before continuing.
In the case of the NOP instruction, the second value in the second byte is the "base" register of a combined base register, displacement register and offset address. If the base register is also 0, the branch is not taken regardless of the value of the displacement register or displacement address. NOPR 2 0x0700 or 0x070n or 0x07n0 where "n" is any 4-bit value. LoongArch NOP 4 0x03400000 Opcode for andi r0,r0,0, an instruction that bitwise-ANDs the always-0 register with zero. MicroBlaze NOP 4 0x80000000 Opcode for or r0,r0,r0, an instruction that bitwise-ORs the always-0 register with itself.AMD/Xilinx, MicroBlaze Processor Reference Guide, UG984 (v2021.2) October 27, 2021, p. 281 MIPS NOP 4 0x00000000 Stands for sll r0,r0,0, meaning: Logically shift register 0 zero bits to the left and store the result in register 0. Writes to register 0 are ignored; it always contains 0. MIPS-X NOP 4 0x60000019 (extended opcode for add r0,r0,r0) MIX NOP 1 word ± * * * * 0 The * bytes are arbitrary, and can be anything from 0 to the maximum byte (required to be in the range 63-99). MIX uses sign-magnitude representation. MMIX SWYM 4 0xFD****** SWYM stands for "Sympathize with your machinery". The * digits can be chosen arbitrarily. MOS Technology 65xx (e.g. 6502),WDC 65C816 NOP 1 0xEA NOP consumes two clock cycles. Undefined opcodes in the NMOS versions of the 65xx family were converted to be NOPs of varying instruction lengths and cycle times in the 65C02. Motorola 6800 NOP 1 0x01 Motorola 68000 family NOP 2 0x4E71 This synchronizes the pipeline and prevents instruction overlap. TRAPF,TRAPF.L #data 2,4,6 0x51FC, Trap if false.
Suggested opcode for 68020 and later 68k processors if a NOP without pipeline synchronization is desired. ('n' may take any 4-bit value.) Motorola 6809 NOP 1 0x12 Motorola 88000 family BCND lt0,r0,X,ADD r0,r0,r0,TB1 0,r0,x 4 0xE980xxxx,0xF4007000,0xF000D8xx Branch if always-0 register is less than 0,Add always-0 register to itself,Trap if bit 0 of always-0 register is 1 (serializing). MSP430 NOP 2 0x4303 Opcode for mov #0,r3 or mov r3,r3, an instruction that performs a move from a "constant generation register" to itself. PA-RISC NOP 4 0x08000240 Opcode for OR 0,0,0. LDI 26,0 4 0x34000034 Palindromic NOP – that is, an instruction that executes as NOP regardless of whether byte order is interpreted as little-endian or big-endian. Some PA-RISC system instructions are required to be followed by seven palindromic NOPs. PDP-6, PDP-10 JFCL 0, (conventional)JUMP, SETA, SETAI, CAI, TRN, TLN 1 word 25500******* (octal) Jump neverJump never, set nothing, skip never PDP-11 NOP 2 000240 (octal) Clear none of the condition codes PDP-8 NOP 1 word (12 bits) 7000 (octal) OPR with no action bits set PIC microcontroller NOP 12 bits 0b000000000000 Number of bits in NOP varies by series. POWER, PowerPC, Power ISA NOP 4 0x60000000 Opcode for ori r0,r0,0.
Under the Power ISA, many apparent no-op instruction encodings have significant side-effects – therefore, no-op encodings other than should be carefully avoided unless these side-effects are specifically intended. For example: ori r31,r31,0 is a serializing instruction. or rX,rX,rX with X=1,2,3,5,6,7 or 31 sets thread priority based on X. or r26,r26,r26 is a memory store writeback hint. xori r0,r0,0 is an explicitly unoptimized no-op for use in timing-loops. and rX,rX,rX with X=0,1 are performance-probe no-ops. or rX,rX,rX with X=28,29,30,31 will stall instruction dispatch for a fixed number of CPU cycles on IBM PPE based processors.