Integrated circuits and certain other electronic components are put into protective packages to allow easy handling and assembly onto printed circuit boards and to protect the devices from damage. A very large number of package types exist. Some package types have standardized dimensions and tolerances, and are registered with trade industry associations such as JEDEC and Pro Electron. Other types are proprietary designations that may be made by only one or two manufacturers. Integrated circuit packaging is the last assembly process before testing and shipping devices to customers.

Occasionally specially-processed integrated circuit dies are prepared for direct connections to a substrate without an intermediate header or carrier. In flip chip systems the IC is connected by solder bumps to a substrate. In beam-lead technology, the metallized pads that would be used for wire bonding connections in a conventional chip are thickened and extended to allow external connections to the circuit. Assemblies using "bare" chips have additional packaging or filling with epoxy to protect the devices from moisture.

Through-hole packages

Through-hole technology uses holes drilled through the printed circuit board (PCB) for mounting the components. The component has leads that are soldered to pads on the PCB to electrically and mechanically connect them to the PCB.

Acronym Full name Remark SIP Single in-line package DIP Dual in-line package pin spacing, rows or apart. Other row spacings are used much less frequently, like and . CDIP Ceramic DIP CERDIP Glass-sealed ceramic DIP QIP Quad in-line package Like DIP but with staggered (zig-zag) pins. SKDIP Skinny DIP Standard DIP with pin spacing, rows apart. SDIP Shrink DIP Non-standard DIP with smaller pin spacing. ZIP Zig-zag in-line package MDIP Molded DIP PDIP Plastic DIP

Surface mount

Acronym Full name Remark CCGA Ceramic column-grid array (CGA) CGA Column-grid array CERPACK Ceramic package CQGP Ceramic Quad Grid Array Package LLP Lead-less lead-frame package A package with metric pin distribution (0.5–0.8 mm pitch) LGA Land grid array LTCC Low-temperature co-fired ceramic MCM Multi-chip module MICRO SMDXT Micro surface-mount device extended technology

Chip on board is a packaging technique that directly connects a die to a PCB, without an interposer or lead frame.

Chip carrier

A chip carrier is a rectangular package with contacts on all four edges. Leaded chip carriers have metal leads wrapped around the edge of the package, in the shape of a letter J. Leadless chip carriers have metal pads on the edges. Chip carrier packages may be made of ceramic or plastic and are usually secured to a printed circuit board by soldering, though sockets can be used for testing.

Acronym Full name Remark BCC Bump chip carrier CLCC Ceramic lead-less chip carrier LCC Lead-less chip carrier Contacts are recessed vertically. LCC Leaded chip carrier LCCC Leaded ceramic-chip carrier DLCC Dual lead-less chip carrier (ceramic) PLCC Plastic leaded chip carrier

Pin grid arrays

Acronym Full name Remark OPGA Organic pin-grid array FCPGA Flip-chip pin-grid array PGA Pin-grid array Also known as PPGA CPGA Ceramic pin-grid array

Flat packages

Acronym Full name Remark – Flat-pack Earliest version metal/ceramic packaging with flat leads CFP Ceramic flat-pack CQFP Ceramic quad flat-pack Similar to PQFP BQFP Bumpered quad flat-pack DFN Dual flat-pack No lead ETQFP Exposed thin quad flat-package PQFN Power quad flat-pack No-leads, with exposed die-pad[s] for heatsinking PQFP Plastic quad flat-package LQFP Low-profile quad flat-package QFN Quad flat no-leads package Also called as micro lead frame (MLF). QFP Quad flat package MQFP Metric quad flat-pack QFP with metric pin distribution HVQFN Heat-sink very-thin quad flat-pack, no-leads SIDEBRAZE TQFP Thin quad flat-pack VQFP Very-thin quad flat-pack TQFN Thin quad flat, no-lead VQFN Very-thin quad flat, no-lead WQFN Very-very-thin quad flat, no-lead UQFN Ultra-thin quad flat-pack, no-lead ODFN Optical dual flat, no-lead IC packaged in transparent packaging used in optical sensor

Small outline packages A small outline integrated circuit (SOIC) is a surface-mounted integrated circuit (IC) package which occupies an area about 30–50% less than an equivalent dual in-line package (DIP), with a typical thickness being 70% less. They are generally available in the same pin-outs as their counterpart DIP ICs. Acronym Full name Remark SOP Small-outline package CSOP Ceramic small-outline package DSOPDual small-outline package HSOP Thermally-enhanced small-outline package HSSOPThermally-enhanced shrink small-outline package HTSSOPThermally-enhanced thin shrink small-outline package mini-SOIC Mini small-outline integrated circuit MSOP Mini small-outline package Maxim uses the trademarked name μMAX for MSOP packages PSOP Plastic small-outline package PSON Plastic small-outline no-lead package QSOP Quarter-size small-outline package The terminal pitch is 0.635 mm. SOIC Small-outline integrated circuit Also known as SOIC NARROW and SOIC WIDE SOJ Small-outline J-leaded packageSONSmall-outline no-lead package SSOP Shrink small-outline package TSOP Thin small-outline package TSSOP Thin shrink small-outline package TVSOP Thin very-small-outline package VSOPVery-small-outline packageVSSOPVery-thin shrink small-outline packageAlso referred as MSOP = micro small-outline package WSON Very-very-thin small-outline no-lead package USON Very-very-thin small-outline no-lead package Slightly smaller than WSON

Chip-scale packages

According to IPC's standard J-STD-012, Implementation of Flip Chip and Chip Scale Technology, in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1 mm.

Acronym Full name Remark BL Beam lead technology Bare silicon chip, an early chip-scale package CSP Chip-scale package Package size is no more than 1.2× the size of the silicon chip TCSP True chip-size package Package is same size as silicon TDSP True die-size package Same as TCSP WCSP or WL-CSP or WLCSP Wafer-level chip-scale packageA WL-CSP or WLCSP package is just a bare die with a redistribution layer (or I/O pitch) to rearrange the pins or contacts on the die so that they can be big enough and have sufficient spacing so that they can be handled just like a BGA package.Application note nxp.com PMCP Power mount CSP (chip-scale package) Variation of WLCSP, for power devices like MOSFETs. Made by Panasonic. Fan-out WLCSP Fan-out wafer-level packaging Variation of WLCSP. Like a BGA package but with the interposer built directly atop the die and encapsulated alongside it. eWLB Embedded wafer level ball grid array Variation of WLCSP. MICRO SMD - Chip-size package (CSP) developed by National Semiconductor COB Chip on board Bare die supplied without a package. It is mounted directly to the PCB using bonding wires and covered with a blob of black Epoxy. Also used for LEDs. In LEDs, transparent epoxy or a silicon caulk-like material that may contain a phosphor is poured into a mold containing the LED(s) and cured. The mold forms part of the package. COF Chip-on-flex Variation of COB, where a chip is mounted directly to a flex circuit. Unlike COB, it may not use wires nor be covered with epoxy, using underfill instead. TAB Tape-automated bonding Variation of COF, where a flip chip is mounted directly to a flex circuit without the use of bonding wires. Used by LCD driver ICs. COG Chip-on-glass Variation of TAB, where a chip is mounted directly to a piece of glass - typically an LCD. Used by LCD and OLED driver ICs.

Ball grid array

Ball grid array (BGA) uses the underside of the package to place pads with balls of solder in grid pattern as connections to PCB.

Acronym Full name Remark FBGA Fine-pitch ball-grid array A square or rectangular array of solder balls on one surface LBGA Low-profile ball-grid array Also known as laminate ball-grid array TEPBGA Thermally-enhanced plastic ball-grid array CBGA Ceramic ball-grid array OBGA Organic ball-grid array TFBGA Thin fine-pitch ball-grid array PBGA Plastic ball-grid array MAP-BGA Mold array process - ball-grid array UCSP Micro (μ) chip-scale package Similar to a BGA (A Maxim trademark example) μBGA Micro ball-grid array Ball spacing less than 1 mm LFBGA Low-profile fine-pitch ball-grid array TBGA Thin ball-grid array SBGA Super ball-grid array Above 500 balls UFBGA Ultra-fine ball-grid array

Transistor, diode, small-pin-count IC packages

MELF: Metal electrode leadless face (usually for resistors and diodes) SOD: Small-outline diode SOT: Small-outline transistor (also SOT-23, SOT-223, SOT-323) TO-XX: wide range of small pin count packages often used for discrete parts like transistors or diodes TO-3: Panel-mount with leads TO-5: Metal can package with radial leads TO-18: Metal can package with radial leads TO-39: Similar to TO-5 with shorter leads TO-46: Similar to TO-18 with lower cap height TO-66: Similar shape to the TO-3 but smaller TO-92: Plastic-encapsulated package with three leads TO-99: Metal can package with eight radial leads TO-100: Metal can package with ten radial leads, similar to TO-99 TO-126: Plastic-encapsulated package with three leads and a hole for mounting on a heat sink TO-220: Through-hole plastic package with a (usually) metal heat sink tab and three leads TO-226 TO-247: Plastic-encapsulated package with three leads and a hole for mounting on a heat sink TO-251: Also called IPAK: SMT package similar to the DPAK but with longer leads for SMT or TH mounting TO-252: (also called SOT428, DPAK): TO-262: Also called I2PAK: SMT package similar to the D2PAK but with longer leads for SMT or TH mounting TO-263: Also called D2PAK: SMT package similar to the TO-220 without the extended tab and mounting hole TO-274: Also called Super-247: SMT package similar to the TO-247 without the mounting hole

Dimension reference

Surface-mount

Through-hole

Package dimensions All measurements below are given in mm. To convert mm to mils, divide mm by 0.0254 (i.e., 2.54 mm / 0.0254 = 100 mil).

C Clearance between package body and PCB. H Height of package from pin tip to top of package. T Thickness of pin. L Length of package body only. LW Pin width. LL Pin length from package to pin tip. P Pin pitch (distance between conductors to the PCB). WB Width of the package body only. WL Length from pin tip to pin tip on the opposite side.

Dual row Image Family Pin Name Package L WB WL H C P LL T LW DIP rowspan=2 Dual inline package 8-DIP 9.2–9.8 6.2–6.48 7.62 7.7 2.54 (0.1in) 3.05–3.6 1.14–1.73 32-DIP 15.24 2.54 (0.1in) LFCSP Lead-frame chip-scale package 0.5 MSOP rowspan=3 Mini small-outline package 8-MSOP 3 3 4.9 1.1 0.10 0.65 0.95 0.18 0.17–0.27 10-MSOP 3 3 4.9 1.1 0.10 0.5 0.95 0.18 0.17–0.27 16-MSOP 4.04 3 4.9 1.1 0.10 0.5 0.95 0.18 0.17–0.27 SOSOICSOP rowspan=4 Small-outline integrated circuit 8-SOIC 4.8–5.0 3.9 5.8–6.2 1.72 0.10–0.25 1.27 1.05 0.19–0.25 0.39–0.46 14-SOIC 8.55–8.75 3.9 5.8–6.2 1.72 0.10–0.25 1.27 1.05 0.19–0.25 0.39–0.46 16-SOIC 9.9–10 3.9 5.8–6.2 1.72 0.10–0.25 1.27 1.05 0.19–0.25 0.39–0.46 16-SOIC 10.1–10.5 7.5 10.00–10.65 2.65 0.10–0.30 1.27 1.4 0.23–0.32 0.38–0.40 SOT Small-outline transistor SOT-23-6 2.9 1.6 2.8 1.45 0.95 0.6 0.22–0.38 SSOP Shrink small-outline package 0.65 TDFN Thin dual flat no-lead 8-TDFN 3 3 3 0.7–0.8 0.65 0.19–0.3 TSOP Thin small-outline package 0.5 TSSOP Thin shrink small-outline package 8-TSSOP 2.9-3.1 4.3-4.5 6.4 1.2 0.15 0.65 0.09–0.2 0.19–0.3Y14-TSSOP4.9-5.14.3-4.56.41.10.05-0.150.650.09-0.20.19-0.3020-TSSOP6.4-6.64.3-4.56.41.1.05-0.150.650.09-0.20.19-0.30 μSOP Micro small-outline packagePackage outline maximintegrated.com μSOP-8 3 4.9 1.1 0.65 US8 US8 package 2 2.3 3.1 .7 0.5