The ND-500 was a 32-bit superminicomputer delivered in 1981 by Norsk Data priced from £ for the base model. It relied on a ND-100 to do housekeeping tasks and run the OS, SINTRAN III. A configuration could feature up to four ND-500 CPUs in a shared-memory configuration.
System architecture The ND-500 combined a 32-bit system based on one or more Nord-500 or ND-500 processors with a ND-100 minicomputer responsible for input/output handling, job scheduling, management of the ND-500 system, and providing a multi-user environment based on the SINTRAN III/VS operating system. This arrangement largely preserved the general architecture of systems based on the preceding Nord-5 and Nord-50 models, and in keeping with those models, the 32-bit component of the ND-500 was aimed at "simulation, numerical analysis and scientific" workloads.
The ND-500 processor employed split data and instruction caches, running with a 110 nanosecond cycle time, along with similarly separated memory management units, thus permitting access to a full 32-bit address space for both program instructions and data. A total 32 MB of physical memory was supported. Physical memory was shared between the ND-100 and ND-500 systems, exposed in a "multiport" arrangement, with the ND-500 having two paths to this RAM, the ND-100 having one path, and the direct memory access hardware having its own path. A prefetch processor was used to decode instructions fetched from memory, to populate the execution pipeline, and to initiate memory accesses for referenced addresses. This processor operated concurrently with the arithmetic logic unit.
Processor architecture The instruction set of the ND-500, featuring "184 basic instruction codes" specialised by several data types and addressing modes, along with "few and specialized" registers, lent itself to an instruction encoding of only one or two bytes, albeit with the potential for several accompanying operands, up to 256 in number. Operands could be from one to nine bytes in length, and thus the documentation for the ND-500 notes, "The shortest instructions are one byte long, the longest may be several thousand bytes long." This contrasted strongly with the design of the CPU in its predecessor, the Nord-50, which featured 32-bit instructions in only three formats and the availability of 64 general-purpose registers.
The ND-500 processor provides only four 32-bit registers for use as integer accumulators or index registers, I1 through I4, and four 32-bit registers for use as floating-point accumulators, A1 through A4, each extended by one of four extension registers, E1 through E4, to provide 64-bit registers for double-precision floating-point operations. Base registers B and R provide access to local variables and record storage respectively. Several other special-purpose registers are provided such as the program counter (P), link or subroutine return address (L), top-of-stack (TOS), plus registers related to trap handling, processor status, and process characteristics. Of the 50 documented registers in the ND-500, several are reserved for use by the processor's microprogram.
Thus, in its selection of registers, the ND-500 processor more strongly resembles the ND-100 which, at each priority level, provides a single accumulator (A), index register (X), base register (B), extension register (D), program counter (P), link register (L), along with a temporary register (T) mostly used for floating-point operations, and a status register (STS). Unlike the ND-500, the ND-100 preserves the fixed-size, 16-bit instruction format of the earlier Nord-10 series, but like the ND-500, the ND-100 processor is microprogrammed.
Promotional materials for the ND-500 emphasised the "highly symmetric" or orthogonal instruction set, permitting the use of all addressing modes with all instruction types and with all data types, providing memory-to-memory instructions able to retrieve operands, perform computational operations, and store results. Such materials claimed a higher code density than most 16-bit computers despite the 32-bit nature of the ND-500 processor.
The ND-5000 architecture introduced various refinements, notably a four-stage pipeline, allowing the constituent parts of each microcode instruction, or "microinstruction", to be processed in turn by dedicated processing units in the pipeline. The four pipeline stages involve instruction fetching, operand fetching, ALU operations, and result writing. Thus, up to four microinstructions could be undergoing processing at once, potentially permitting an execution throughput of one microinstruction per machine cycle. Although the most frequently used machine instructions or "macroinstructions" were implemented by a single microinstruction at each pipeline stage, potentially delivering a throughput of one machine instruction per cycle, a number of factors could contribute to a lower throughput, notably cache misses for instructions, addresses and data, the use of indirect and indexed addressing, data alignment issues, and incorrect branch predictions. Cycles could be added or stretched to accommodate these complicating conditions.
The cache architecture of the ND-500 employed virtual addresses instead of physical addresses to allow cache lookup and address translation to occur in parallel, a strategy also employed by the PA-RISC architecture. The ND-500 architecture employed a "write-through" cache strategy, but a small, high-speed write buffer allowed the processor to proceed while the cache controller populated the cache and issued writes to memory.
The ND-5000 cache implementation differed from that of the ND-500, employing a "write-once" strategy that issued a memory write when first recording data to be stored in the cache for a particular location. Such an approach aimed to achieve the efficiency of a write-back strategy by largely avoiding main memory access. However, a write-back strategy with the virtually addressed cache was regarded as presenting difficulties should a write-back to memory occur at a later point in time and cause a page fault. The write-once approach avoided such complications by establishing an initial memory mapping and reserving it for eventual writes to memory. A write-through strategy could also be selected through a processor configuration register.
Hardware implementations In its first incarnation, the ND-500 was built using TTL integrated circuits, just as the Nord-50 had been. The floating-point processor featured in the ND-500 reportedly consisted of 579 integrated circuits and used a combinatorial approach to support the execution of 64-bit multiplication operations in 480 nanoseconds. Norsk Data claimed a Whetstone benchmark rating of 1.4 to 1.8 million single-precision Whetstone instructions per second for the ND-500.
The ND-500 architecture lived through four distinct implementations. Each implementation was sold under a variety of different model numbers.
ND also sold multiprocessor configurations, naming them ND-580/n and an ND-590n, where n represented the number of CPUs in a given configuration, 2, 3, or 4.
ND-500/1 Sold as the ND-500, ND-520, ND-540, and ND-560.
ND-500/2 Sold as the ND-570, ND-570/CX, and ND-570/ACX.
The ND-500/CX series upgraded the ND-500 range during 1984, introducing the ND-530/CX, ND-550/CX, ND-560/CX and ND-570/CX in a range of different product variants, including the compact model III for the lower-end products. Advertised performance figures were given as 0.6, 1.3, 2.1 and 3.3 million Whetstone instructions per second for the respective products. Pricing for the models was given as ranging from $ for the ND-530/CX to $ for the ND-570/CX, these prices also including 24 terminals and a printer. A basic ND-570/CXA configuration cost around $ when announced in late 1983.
ND-505 The ND-505/CX was a version of the ND-500 machine with an advertised 29-bit addressing capability. Pins were essentially snipped on the backplane, removing its status as a superminicomputer, and allowing it to legally pass the CoCom embargo in force at the time and be exported to the Eastern Bloc. Disputed claims were made in Computerworld's Norwegian edition that the ND-505 was, in fact, a machine capable of 31-bit addressing, with the segment size halved by cutting a connection corresponding to the top bit of the segment address.
Since the ND-500 architecture provides 32 segments per domain and has separate address spaces for instructions and data, usually employing a 27-bit segment size of 128 MB and yielding instruction and data areas each of 4 GB in size, a halved segment size of 64 MB would have yielded instruction and data areas each of 2 GB in size. However, the advertised sizes of these areas for the ND-505 was only 0.25 GB, suggesting 28-bit addressing and thus further restrictions on the number of signals provided for the segment address or for segment selection. Meanwhile, the size of the combined 28-bit instruction and data areas could, with some generosity, be regarded as being equivalent to a 29-bit address space in architectures that do not maintain such a separate addressing regime, at least for the purposes of advertising.
KPS-10 The KPS-10 in the Knowledge Processing System range developed by Racal-Norsk, a joint venture with Racal Electronics, was based on the ND-570 model, featuring customised microcode to run ZetaLisp and other languages at potentially higher speeds than existing Lisp machines and Digital's VAX. Several of these systems were reportedly delivered to "universities in the UK and Scandinavia" in advance of a commercial launch scheduled for late 1985.
The KPS-10 employed framebuffers arranged as bit planes in dedicated graphics boards that were mapped into the memory of the system processor, permitting the processor to update the display by writing to the memory region exposed for each bit plane. Each graphics board contained one megabyte of memory divided into four bit planes whose data could be used to represent monochrome, greyscale and colour displays, with the latter involving a colour controller employing a colour lookup table and digital-to-analogue converters to generate colour signals. Pairs of framebuffers could be combined to provide double buffering. A display of could reportedly be updated in "less than a microsecond". The memory architecture of the machine, featuring "an internal communications bus that requires more than 100 balanced line drivers and receivers to handle the address, data, and control lines" was described as ideal for transmitting graphical data to terminals at a distance of 100 metres from the computer itself, and the utilisation of several of the machine's ten memory banks permitted a theoretical limit of 36 bitmapped screens and a practical limit of 20 bitmapped screens.
A KPS-5 model based on the ND-550 was also announced but presumably never delivered. Racal and Norsk Data abandoned their joint venture in early 1986 claiming that the investment required to develop artificial intelligence systems was "not commercially justified at present".
Samson Sold as the ND-5200, ND-5400, ND-5500, ND-5700, ND-5800 and ND-5900. The ND-120 CPU line, which constituted the ND-100 side of the three higher-end ND-5000 computers, was named Delilah. The ND-110 accompanied the three lower-end models. As the 500/5000 line progressed in speed, the dual-arch ND-100/500 configuration increasingly became bottlenecked by all input/output (I/O) having to go through the ND-100.