The Intel 486, officially named i486 and also known as 80486, is a microprocessor introduced in 1989. It is a higher-performance follow-up to the Intel 386. It represents the fourth generation of binary compatible CPUs following the 8086 of 1978, the Intel 80286 of 1982, and 1985's i386.
It was the first tightly-pipelined x86 design as well as the first x86 chip to include more than one million transistors. It offered a large on-chip cache and an integrated floating-point unit. When it was announced, the initial performance was originally published between 15 and 20 VAX MIPS, between 37,000 and 49,000 dhrystones per second, and between 6.1 and 8.2 double-precision megawhetstones per second for both 25 and 33 MHz version. A typical 50 MHz i486 executes 41 million instructions per second Dhrystone MIPS and SPEC integer rating of 27.9.Chen, Allan, "The 50-MHz Intel486 Microprocessor", Intel Corporation, Microcomputer Solutions, September/October 1991, page 2. It is approximately twice as fast as the i386 or i286 per clock cycle. The i486's improved performance is thanks to its five-stage pipeline with all stages bound to a single cycle. The enhanced FPU unit on the chip was significantly faster than the i387 FPU per cycle. The i387 FPU was a separate, optional math coprocessor installed in a motherboard socket alongside the i386.
The i486 was succeeded as the series flagship by the original Pentium in 1993 while the Celeron took over as the low-end series in 1998. Orders were discontinued for the i486 on March 30, 2007, and the last shipments were on September 28, 2007.
History The concept of this microprocessor generation was discussed with Pat Gelsinger and John Crawford shortly after the release of 386 processor in 1985. The team started the computer simulation in early 1987. They finalized the logic and microcode function during 1988. The team finalized the database in February 1989 until the tape out on March 1. They received the first silicon from the fabrication on March 20.Chen, Allan, "Designing A Mainframe on a Chip: Interview with the i486 Microprocessor Design Team", Intel Corporation, Microcomputer Solutions, July/August 1989, page 12.
The i486 was announced at Spring Comdex on April 10, 1989. At the announcement, Intel stated that samples would be available in the third quarter and production quantities would ship in the fourth quarter.486 32-bit CPU breaks new ground in chip density and operating performance. (Intel Corp.) (product announcement) EDN, May 11, 1989, Pryce, Dave. The first i486-based PCs were announced in late 1989.
In fall of 1991, Intel introduced the 50 MHz i486 DX using the three layer 800 nm process CHMOS-V technology. They were available for US$665 in 1,000-unit quantities.
In that season, Intel introduced a low-power 25 MHz Intel486 DX microprocessor. This processor was available for US$471. Also, there were low-power 16, 20, and 25 MHz Intel 486SX microprocessors. They were available at $235, $266, and $366 for these frequency range respectively. All pricing were in quantities of 1,000 pieces. These low-power microprocessors have power consumption reduced by 50–75% compared to similar regular versions of these CPUs.Intel Corporation, "New Product Focus: Components: Modified Chips Cuts Portable Power Consumption", Microcomputer Solutions, November/December 1991, page 10.
The first major update to the i486 design came in March 1992 with the release of the clock-doubled 486DX2 series. It was the first time that the CPU core clock frequency was separated from the system bus clock frequency by using a dual clock multiplier, supporting 486DX2 chips at 40 and 50 MHz. The faster 66 MHz 486DX2-66 was released that August.
The fifth-generation Pentium processor launched in 1993, while Intel continued to produce i486 processors, including the triple-clock-rate 486DX4-100 with a 100 MHz clock speed and a L1 cache doubled to 16 KB.
Earlier, Intel had decided not to share its 80386 and 80486 technologies with AMD. However, AMD believed that their technology sharing agreement extended to the 80386 as a derivative of the 80286. AMD reverse-engineered the 386 and produced the 40 MHz Am386DX-40 chip, which was cheaper and had lower power consumption than Intel's best 33 MHz version. Intel attempted to prevent AMD from selling the processor, but AMD won in court, which allowed it to establish itself as a competitor.
After 386 competitors appeared, Intel in 1992 lowered the price of the 25-MHz 80486SX to less than that of the 33-MHz 80386. An industry analyst said that Intel wanted customers to move to the competition-free 486. The strategy was very successful; by 1993 Dell reported that 80486-based computers were 70% of sales. AMD continued to create clones, releasing the first-generation Am486 chip in April 1993 with clock frequencies of 25, 33 and 40 MHz. Second-generation Am486DX2 chips with 50, 66 and 80 MHz clock frequencies were released the following year. The Am486 series was completed with a 120 MHz DX4 chip in 1995.
AMD's long-running 1987 arbitration lawsuit against Intel was settled in 1995, and AMD gained access to Intel's 80486 microcode. This led to the creation of two versions of AMD's 486 processor one reverse-engineered from Intel's microcode, while the other used AMD's microcode in a clean-room design process. However, the settlement also concluded that the 80486 would be AMD's last Intel clone.
Another 486 clone manufacturer was Cyrix, which was a fabless co-processor chip maker for 80286/386 systems. The first Cyrix 486 processors, the 486SLC and 486DLC, were released in 1992 and used the 80386 package. Both Texas Instruments-manufactured Cyrix processors were pin-compatible with 386SX/DX systems, which allowed them to become an upgrade option. However, these chips could not match the Intel 486 processors, having only 1 KB of cache memory and no built-in math coprocessor. In 1993, Cyrix released its own Cx486DX and DX2 processors, which were closer in performance to Intel's counterparts. Intel and Cyrix sued each other, with Intel filing for patent infringement, and Cyrix for antitrust claims. In 1994, Cyrix won the patent infringement case and dropped its antitrust claim.
In 1995, both Cyrix and AMD began looking at a ready market for users wanting to upgrade their processors. Cyrix released a derivative 486 processor called the 5x86, based on the Cyrix M1 core, which was clocked up to 120 MHz and was an option for 486 Socket 3 motherboards. AMD released a 133 MHz Am5x86 upgrade chip, which was essentially an improved 80486 with double the cache and a quad multiplier that also worked with the original 486DX motherboards. Am5x86 was the first processor to use AMD's performance rating and was marketed as Am5x86-P75, with claims that it was equivalent to the Pentium 75. Kingston Technology launched a "TurboChip" 486 system upgrade that used a 133 MHz Am5x86.
Intel responded by making a Pentium OverDrive upgrade chip for 486 motherboards, which was a modified Pentium core that ran up to 83 MHz on boards with a 25 or 33 MHz front-side bus clock. OverDrive wasn't popular due to speed and price. New computers equipped with 486 processors in discount warehouses became scarce, and an IBM spokesperson called it a "dinosaur". Even after the Pentium series of processors gained a foothold in the market, however, Intel continued to produce 486 cores for industrial embedded applications. Intel discontinued production of i486 processors in late 2007.
Improvements
+ i486 registers 31 ... 15 ... 07 ... 00 (bit position) Main registers (8/16/32 bits) EAX AH AL A register EBX BH BL B register ECX CH CL C register EDX DH DL D register Index registers (16/32 bits) ESI SI Source Index EDI DI Destination Index EBP BP Base Pointer ESP SP Stack Pointer Program counter (16/32 bits) EIP IP Instruction Pointer Segment selectors (16 bits) CS Code Segment DS Data Segment ES Extra Segment FS F Segment GS G Segment SS Stack Segment Status register 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position) V R 0 N IOPL O D I T S Z 0 A 0 P 1 C EFlags Floating-point registers (80 bits) 79 ... 00 (bit position) ST0 STack register 0 ST1 STack register 1 ST2 STack register 2 ST3 STack register 3 ST4 STack register 4 ST5 STack register 5 ST6 STack register 6 ST7 STack register 7
The instruction set of the i486 is very similar to the i386, with the addition of a few extra instructions, such as CMPXCHG, a compare-and-swap atomic operation, and XADD, a fetch-and-add atomic operation that returned the original value (unlike a standard ADD, which returns flags only). This generation CPU has brought up to 156 different instructions listing.House, Dave, "Putting the RISC vs. CISC Debate to Rest", Intel Corporation, Microcomputer Solutions, November/December 1991, page 18
The i486's performance architecture is a vast improvement over the i386. It has an on-chip unified instruction and data cache, an on-chip floating-point unit (FPU) and an enhanced bus interface unit. Due to the tight pipelining, sequences of simple instructions (such as ALU reg,reg and ALU reg,im) could sustain single-clock-cycle throughput (one instruction completed every clock). In other words, it was running about 1.8 clocks per instruction. These improvements yielded a rough doubling in integer ALU performance over the i386 at the same clock rate. A 16 MHz i486 therefore had performance similar to a 33 MHz i386. The combination of both CPU and FPU housed on a single die results in bus utilization rates of 50% for the 25 MHz Intel486 version.Intel Corporation, "Coming Attractions: Clock-Doubling Technology", Microcomputer Solutions, January/February 1992, page 6 In other words, with the combination of both CPU and MCP (math coprocessor) provides 40% more performance than with both Intel386 DX and Intel387 DX math coprocessor combined.Intel Corporation, "A Guide to the Intel Architecture", Microcomputer Solutions, January/February 1992, page 11 The older design had to reach 50 MHz to be comparable with a 25 MHz i486 part.
Differences between i386 and i486 An 8 KB on-chip (level 1) SRAM cache stores the most recently used instructions and data (16 KB and/or write-back on some later models). The i386 had no internal cache but supported a slower off-chip cache (not officially a level 2 cache because i386 had no internal level 1 cache). An enhanced external bus protocol to enable cache coherency and a new burst mode for memory accesses to fill a cache line of 16 bytes within five bus cycles. The 386 needed eight bus cycles to transfer the same amount of data. Tightly coupled pipelining completes a simple instruction like ALU reg,reg or ALU reg,im every clock cycle (after a latency of several cycles). The i386 needed two clock cycles. Integrated FPU (disabled or absent in SX models) with a dedicated local bus; together with faster algorithms on more extensive hardware than in the i387, this performed floating-point calculations faster than the i386/i387 combination. Improved MMU performance. New instructions: XADD, BSWAP, CMPXCHG, INVD, WBINVD, INVLPG.
Just as in the i386, a flat 4 GB memory model could be implemented. All "segment selector" registers could be set to a neutral value in protected mode, or to zero in real mode, and using only the 32-bit "offset registers" (x86-terminology for general CPU registers used as address registers) as a linear 32-bit virtual address bypassing the segmentation logic. Virtual addresses were then normally mapped onto physical addresses by the paging system except when it was disabled (real mode had no virtual addresses). Just as with the i386, circumventing memory segmentation could substantially improve performance for some operating systems and applications.