V850 is a 32-bit RISC CPU architecture produced by Renesas Electronics for embedded microcontrollers. It was designed by NEC as a replacement for their earlier NEC V60 family, and was introduced shortly before NEC sold their designs to Renesas in the early 1990s. It has continued to be developed by Renesas .
The V850 architecture is a load/store architecture with 32 32-bit general-purpose registers. It features a compressed instruction set with the most frequently used instructions mapped onto 16-bit half-words.
Intended for use in ultra-low power consumption systems, such as those using 0.5 mW/MIPS, the V850 has been widely used in a variety of applications, including optical disk drives, hard disk drives, mobile phones, car audio, and inverter compressors for air conditioners. Today, microarchitectures primarily focus on high performance and high reliability, such as the dual-lockstep redundant mechanism for the automotive industry; and the V850 and RH850 families are comprehensively used in cars.
The V850/RH850 microcontrollers are also used prominently on non-Japanese automobile marques such as Chevrolet, Chrysler, Dodge, Ford, Hyundai, Jeep, Kia, Opel, Range Rover, Renault and Volkswagen Group brands.
Overview
The V850 is the trademark name for a 32-bit RISC CPU architecture for embedded microcontrollers of Renesas Electronics Corporation. It was originally developed and manufactured by NEC Corporation in the early 1990s (the copyright mark for the microcode on the package shows 1991) as a branch of the V800 Series and is still being evolved today.
Its base-architecture has been succeeded by the V850 family variants, named V850E, V850E1, V850ES, V850E1F, V850E2, V850E2M, V850E2S, and the RH850 family (V850E2M, V850E2S, and V850E3) CPU cores.
Many compilers and debuggers are available from various development tool vendors.
Real-time operating systems are provided by compiler vendors.
In-circuit emulators (ICE) are provided by many vendors. Legacy proven pod-based types—the JTAG-based N-Wire interface with the N-trace type, and the Nexus interface with the Aurora Trace type—are available.
Application systems
The first V850 CPU core was used in many DVD drives manufactured by NEC's and Sony's Optiarc (later wholly owned by Sony). NEC Electronics (currently Renesas Electronics) itself intensively developed application-specific standard products (ASSPs) for SCOMBO Series optical disk drives. This first generation of processor core was also used for hard disk drives manufactured by Quantum Corporation (see photo).
In 1997, the V850/xxn product line started with the V850/SA1 and the V850/SV1 and expanded its application to ultra-low-power products such as "handy camcorders." It has a main and sub internal oscillator amplifier working from 1.8 V to 3.6 V with external crystal or ceramic resonator. Software STOP mode, whose internal watch timer operates with a 32.768 kHz sub-oscillator, typically consumes only 8μA of electrical current. In 1998, NEC launched the V850/SB1 with IEBus controller, for car audio, an ultra-low-power (3.6 mW@5V/MIPS) and ultra-low-noise (EMI/EMS) 5V product. The V850/SC1 was also for car audio. These strategic product line expansions succeeded in increasing the number of devices sold.
The first generation of the V850 core is also used for some NEC mobile phones. It is also used for the programmable-host CPUs of some small form factor GSM/GPRS mobile devices with GPS embedded modem modules.
In the next phase, NEC targeted the automotive industry with a CAN bus controller based on the V850 as the V850/SF1. Later on, the automotive industry became the main target of the V850 and RH850.
The V850E core was targeted at system-on-a-chip (SoC) applications as well as standard products, and was used for some Japanese domestic mobile phones, including Sony Mobile's and NEC's. V850E and V850ES are also used in air conditioning inverter compressors. At this stage, another mass market was its use in car audio. The V850ES core succeeded in the low-power embedded-product line, and is ISA-compatible with the V850E. NEC Electronics (currently, Renesas Electronics) adopted the V850 CPU core for its USB 3.0 controllers.
Around 2005, several companies started a feasibility study for the FlexRay controller on the V850E platform. Yokogawa Digital Computer (currently DTS INSIGHT) developed an evaluation board named GT200 with a V850E/IA1 and a field-programmable gate array (FPGA), which employs the FlexRay controller developed by Bosch.
The V850E2 core primarily targeted automotive areas, but was also used for NEC's mobile phones.
The V850 family lineup (based on V850E, V850ES, and V850E2 cores) and the Renesas RH850 family (based on the V850E3 core, as of 2018) are mainly employed in automotive applications as well as inter-equipment connectivity and motor-control specific microcontroller units (MCUs).
Trademark strategy
The V850 is an unregistered trademark but not a registered one. NEC once applied for a trademark to be registered with the Japan Patent Office, but it was rejected, as it was a natural extension of the series number. However, this action has been enough to prevent other people or organizations from registering it as a trademark. In addition, Renesas has been using the V850X/xxn type trademark, such as V850E/MA1, for more than 20 years, because the combination of one alphabetical with two numerical characters cannot be granted as a registered trademark. It is thus free to use without registration.
One exception is V850E/PHO3 (PHOENIX 3, or PHOENIX-FS). Another usage of PHOENIX 3 by Renesas Electronics is the COOL PHOENIX 3, which employs the ARM Cortex-M0 core. PHOENIX 3 is a registered trademark of the 3DO Company as USPTO Reg. 2,009,119.
According to current Renesas Electronics documentation, at least the following strings are regarded as its trademark: "V800 Series", "V850 family", "V850/SA1", "V850/SB1", "V850/SB2", "V850/SF1", "V850/SV1", "V850E/MA1", "V850E/MA2", "V850E/IA1", "V850E/IA2", "V850E/MS1", "V850E/MS2", "V851", "V852", "V853", "V854", "V850", "V850E", and "V850ES".
Because the V850 trademark has been used for more than 20 years, most people do not know that the RH850 family is based on an extension of the V850 instruction set architecture, and has backward compatibility with V850, V850E, V850ES, and V850E2. The RH850 is consequently thought of as being without the legacy software compatibility of the V850.
Development methodology
Because the V850 family was developed as a branch of the V800 series, the basic CPU architecture is inherited from the V810. The instruction set architecture of the first V850 is drastically modified from that of the V810, but the difference is within a patch level from the GNU Compiler Collection point of view. The main purpose of this change is to implement saturation arithmetic at customers' request.
The detailed design methodology of the V810 is described in this journal. The V850 utilizes these design assets; but the datapath logic was changed from dynamic logic to static logic, to enable 32.768 kHz real-time clock frequency operation mode.
The register-transfer level "CPU architecture design" of the V810 is developed with the Functional Description Language (FDL) on the Falcon Simulator software, which are NEC's in-house CAD tools. This methodology is the same as that used for the NEC V60. In the late 1980s, the Verilog HDL had not yet been acquired by Cadence Design Systems. FDL had been used until the middle of the 2000s, and was also used for the development of NEC's super-computer named Earth Simulator.
The difference from V60 is that the circuit diagram was written with a schematic editor, not of Calma but of Mentor Graphics, called NETED, a part of the Design Architect product on Apollo Computer's workstation, which was the major schematic editor at that moment. It enabled designers to generate netlists, such as EDIF and SPICE, for LVS programs like Cadence's Dracula products, and NEC's in-house Zycad netlist for logic simulation. Later on, this circuit diagram of NETED was able to generate a gate-level Verilog HDL netlist for V850.
Most of the register-transfer-level FDL netlist was translated to the gate-level schematic by hand, because the logic synthesis had not yet to be practical. The FDL was precisely divided into datapath and random logic. For the datapath part, the gate-level circuit diagram enabled manually repeated artwork. On the other hand, for the random logic part, logic synthesis was tried for generating gate-level schematic, but it was only about 10% of the total circuit.
In addition, formal verification was also not yet practical, which meant that full regression test by dynamic logic simulation was required for the gate-level netlist to compare with the RTL one. For gate-level logic simulation, NEC's in-house CAD tool V-SIM was usually used. But sometimes a hardware emulator, such as Zycad LE simulation accelerator, was used for this purpose. (Refer to:. In this material, the performance of Zycad LE is compared with NEC's HAL, but initial design decade differs.)
Architecture
Basic architecture
The basis of the V810 and V850 has a typical general-purpose registers-based load/store architecture. There are 32 32-bit general-purpose registers. Register 0 (R0) is fixed as the Zero Register which always contains zero. In the V850, R30 is implicitly used by the sld and sst instructions. 16-bit short-format load/store instructions use element pointer (ep), where the addressing mode comprises the base address register ep and immediate-operand offsets. In V850E or later microarchitectures, R3 is implicitly used by PREPARE/DISPOSE; call stack frame creation; and unwinding instructions, as a stack pointer. Compilers' calling conventions also use R3 as the stack pointer.
The original V850 has a simple 5-stage 1-clock pitch pipeline architecture.<ref name="V810-seminar"/ This is a significant feature of reduced instruction set computers (RISCs). But the object-code size is about half that of the MIPS R3000, because the V810 and V850 adopted 16-bit and 32-bit 2-way form-length instruction formats, respectively, and most of the frequently used instructions are mapped onto a 16-bit half-word. In other words, a 16-bit external bus width is enough to provide instructions continuously without pipeline stalling, which enables low power consumption on the application board, and is suitable for mobile equipment. This concept is similar to Renesas (formerly, Hitachi) SH, ARM Thumb, and MIPS16 instruction set architectures.
In addition, the instruction set is carefully implemented. For example, to execute a function call with a Jump and (Register) Link instruction, which saves the next program counter (PC) on a register (fixed to R31 in V810), is also one of the RISC techniques to reduce the number of instructions. Return from the function can be accomplished by jmp [Rn] (jmp [R31] in V810) instruction. Typical CISC processors use call and return instructions and push the next PC on their stack memory area.
But V810 and V850 have some microarchitecture differences. The V810 adopts a microprogram operation method for some instructions, such as floating-point arithmetic and bit string operations, while the V850 uses a one-hundred-percent hardwired control method. As a result, for example, the first V850 does not have floating-point arithmetic and bit manipulation instruction sets, including the "find first one/zero" (search 1/0; SCH1x/SCH0x), except for "set/clr/negate a bit" (SET1/CLR1/NOT1). Those extended instruction sets are revived in V850E2x extensions.