Ferroelectric flash memory, (ferroelectric NAND, FeNAND, or FeFET-based NAND), is an emerging non-volatile memory technology that incorporates ferroelectric materials (typically doped hafnium oxide, ) into NAND flash-like architectures. It addresses limitations of conventional charge-trap NAND flash, such as high power consumption, limited endurance, and scaling, by leveraging ferroelectric polarization for data storage. Unlike traditional ferroelectric RAM (FeRAM), which uses a one transistor, one capacitor (1T-1C) structure for random-access memory, ferroelectric flash employs ferroelectric field-effect transistors (FeFETs) in string architectures similar to 3D NAND. This enables higher density, lower operating voltages, and potential for multi-level cell (MLC) or triple-level cell (TLC) operation.
Some 20 different architectures were under development as of 2025.
History Research on ferroelectric transistors began in the 1950s–1960s. Practical development stalled due to material incompatibility with CMOS processes. Early prototypes featured a narrow memory window (the write voltage was only slightly higher than the read voltage). This defeated efforts to read and write multiple bits to a single silicon cell.
The discovery of ferroelectricity in doped thin films in 2011 revived interest, as is CMOS-compatible and scalable below 10 nm. Early proposals for FeNAND appeared in the 2000s–2010s, with prototypes using perovskite materials such as PZT or SBT. The shift to enabled 3D integration. Key milestones include:
In 2012, FeFETs were demonstrated at 28 nm In 2021, the first CMOS-compatible FeNAND arrays were reported From 2023–2025, prototypes achieved low-voltage operation, high endurance (>1012 cycles), and multi-bit storage. In 2023, SK Hynix added an insulating layer that trapped charges on top of the during write, creating a hybrid conventional and ferroelectric device that widened the memory window to an acceptable 10.5 volts.
Device physics and operation Ferroelectrics have a stable, polar electrical orientation that an external electric field can switch. Ferroelectric polarity determines whether an applied voltage can drive electron flow through the adjacent channel. Because ferroelectrics can read and write data at lower voltages, the insulating layers that confine cells can be thinner, enabling as many as 1000 cell layers.
Ferroelectric flash relies on FeFETs, where the gate dielectric includes a ferroelectric layer (e.g., HfZrO or HZO). Data storage occurs via reversible polarization states:
Polarization shifts the transistor threshold voltage (V_th), creating distinct "on" and "off" states Reads are non-destructive (current sensing) Writes use low voltages (3–6 V vs. 15–20 V in charge-trap NAND), reducing power consumption
In 3D FeNAND, cells stack vertically like conventional NAND, but ferroelectric gates replace charge-trap layers.
To store or retrieve information from a cell (up to 5 bits), FeNAND uses a vertical "pass voltage" that connects the cells in a column so that it acts like a single wire. To reduce power demand, Samsung replaced the silicon in current-carrying channels with indium-gallium-zinc-oxide, a semiconductor that allows a 96% lower pass current to switch it.
Advantages
Lower power: Reduced program/erase voltages and no high pass disturbance Higher endurance: 109–1012 cycles vs. 103–105 for NAND Faster speeds: Sub-10 ns switching in prototypes Scalability: Potential for >512 layers and TLC/QLC operation Multi-bit capability: Large memory windows (up to 12–17 V in 2025 demos)
Challenges
Retention and fatigue: polarization degradation over cycles; mitigated by gate-stack engineering (e.g., interlayers): Disturbance in strings: Program/erase interference; solved via band engineering or superlattice structures Manufacturing: Precise control of orthorhombic phase; integration with oxide channels (e.g., IGZO) for reliability.
Comparison +Comparison with FeRAMAspectFerroelectric Flash (FeNAND/FeFET NAND)FeRAMStructureFeFET strings (3D vertical NAND-like)1T-1C capacitor arraysDensityHigh (potential Tb/mm2)Low (Mb range, planar limits)ReadNon-destructiveDestructive (write-after-read)Endurance109–1012 cycles>1015 cyclesSpeedns-scale program/erasens-scale, but array-limitedPowerVery low (no high pass voltage)LowStatusResearch/prototypeCommercial (niche)
Applications The technology has potential in AI edge devices, hyperscale storage, and low-latency NVM. Challenges include reliability, scaling, and cost. Ongoing work (IEDM 2024–2025) focuses on hybrid FeNAND and in-memory computing.
See also
Ferroelectric RAM
References
External links