RISC-V instruction listings

The RISC-V instruction set refers to the set of instructions that RISC-V compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor.

RISC-V Integer Instructions The table below contains a list of the RV Integer Instructions. The integer instruction set is divided in the base I part of the ISA that comes in a 32 bit RV32 and 64 bit RV64 version and M, B and Zicond extensions. There is also an A extension for atomic instructions and F and D instructions for floating point operations.

+ RV Integer (pseudo) Instructions Instruction Name Format Extension RV64 Load Byte rd, imm12(rs) I Load Half rd, imm12(rs) I Load Address rd, imm12(rs) I Load Word rd, imm12(rs) I Load Double rd, imm12(rs) Ix Load Byte (U) rd, imm12(rs) I Load Half (U) rd, imm12(rs) I Load Word (U) rd, imm12(rs) Ix Store Byte rs1, imm12(rs2) I Store Half rs1, imm12(rs2) I Store Word rs1, imm12(rs2) I Store Double rs1, imm12(rs2) I x Load Immediate rd, immIAssembler macro, for immediates needing less than 12 bit expands to addi rd zero imm Load Upper Immediate rd, imm20I Add Upper Immediate to Program Counter rd, imm20I MoVe rd, rsIPseudo Instruction. Expands to single instruction. move Sign EXTended least significant Byte rd, rs B move Sign EXTended least significant Half rd, rs B move Sign EXTended least significant Word rd, rs I x move Zero EXTended least significant Byte rd, rs I move Zero EXTended least significant Half rd, rs B move Zero EXTended least significant Word rd, rs B x move with REVersed byte order rd, rs B ZERO Conditional on EQual to Zero or move rd, rs1, rs2 Zicond ZERO Conditional on Not Equal to Zero or move rd, rs1, rs2 Zicond ADD Immediate rd, rs, imm12 I ADD rd, rs1, rs2 I SHift1 ADD rd, rs1, rs2 B SHift2 ADD rd, rs1, rs2 B SHift3 ADD rd, rs1, rs2 B ADD Word(U to double) rd, rs1, rs2 B x SHift1 Word(U in double) Add to double rd, rs1, rs2 B x SHift2 Word(U in double) Add to double rd, rs1, rs2 B x SHift3 Word(U in double) Add to double rd, rs1, rs2 B x ADD Word to Word Immediate rd, rs, imm12 I x ADD Word rd, rs1, rs2 I x SUBtract rd, rs1, rs2 I SUBtract Word rd, rs1, rs2 I x NEGative. rd, rs I NEGative Word rd, rs I x MULtiply rd, rs1, rs2M MULtiply Word rd, rs1, rs2Mx MULtiply High part rd, rs1, rs2M MULtiply High Part Unsignedrd, rs1, rs2M MULtiply High Part Unsigned Signed rd, rs1, rs2M DIVide rd, rs1, rs2M DIVide (U)rd, rs1, rs2M REMainderrd, rs1, rs2M REMainder (U)rd, rs1, rs2M MINimum rd, rs1, rs2B MAXimum rd, rs1, rs2B MINimum (U) rd, rs1, rs2B MAXimum (U)rd, rs1, rs2B Set bit when EQual to Zero rd, rs I Set bit when Not Equal to Zero rd, rs I Set bit when Less Than Immediate rd, rs, imm12 I Set bit when Less Than rd, rs1, rs2 I Set bit when Less Than Immediate (U) rd, rs, imm12 I Set bit when Less Than (U) rd, rs1, rs2 I Bit Extract Immediate rd, rs, imm5/6 B Bit Extract rd, rs1, rs2 B AND Immediate rd, rs, imm12 I AND rd, rs1, rs2 I AND Not rd, rs1, rs2 B Bit CLeaR Immediate rd, rs, imm5/6 B Bit CLeaR rd, rs1, rs2 B OR Immediate rd, rs, imm12 I OR rd, rs1, rs2 I OR Not rd, rs1, rs2 B Bit SET Immediate rd, rs, imm5/6 B Bit SET rd, rs1, rs2 B eXclusive OR Immediate rd, rs, imm12 I eXclusive OR rd, rs1, rs2 I Not XOR rd, rs1, rs2 B Bit INVert Immediate rd, rs, imm5/6 B Bit INVert rd, rs1, rs2 B NOT rd, rs I OR Combine within Bytesrd, rsB Shift Left Logical Immediate rd, rs, imm5/6 I Shift Left Logical rd, rs1, rs2 I Shift Left Logical Word Immediate rd, rs, imm5 I x Shift Left Logical Word rd, rs1, rs2 I x Shift Left Logical Word (U in double) Immediate rd, rs, imm5/6 I x Shift Right Logical Immediate rd, rs, imm5/6 I Shift Right Logical rd, rs1, rs2 I Shift Right Logical Word Immediate rd, rs, imm5 I x Shift Right Logical Word rd, rs1, rs2 I x Shift Right Arith Immediate rd, rs, imm5/6 I Shift Right Arithmetic rd, rs1, rs2 I Shift Right Arith Word Immediate rd, rs, imm5 I x Shift Right Arithmetic Word rd, rs1, rs2 I x ROtate Right Immediate rd, rs, imm5/6 B ROtate Right rd, rs1, rs2 B ROtate Left rd, rs1, rs2 B ROtate Right Immediate Word rd, rs, imm5 Bx ROtate Right Word rd, rs1, rs2 B x ROtate Left Word rd, rs1, rs2 B x Count Leading Zeros rd, rs B Count Leading Zeros in Word rd, rs B x Count Trailing Zeros rd, rs B Count Trailing Zeros in Word rd, rs B x Count POPulation of 1s rd, rs B Count POPulation of 1s in Word rd, rs Bx Jump label I Jump And Link rd, imm20 I Jump Register rs [, imm12] I Jump And Link Register rd rs [, imm12] I CALL symbol IAssembler macro clobbering ra. Interacts with the loader symbol relocation. Expands to jal ra, imm or auipc ra, imm; jalr ra, ra imm combination TAIL call symbol IAssembler macro, may clobber t1. Interacts with the loader symbol relocation. Expands to jal zero imm or auipc t1, imm; jalr zero t1, imm combination RETurn - IPseudo instruction clobbering ra. Expands to jal zero, ra, 0 Branch == rs1, rs2, label I Branch != rs1, rs2, label I Branch < rs1, rs2, label I Branch > rs1, rs2, label I Branch >= rs1, rs2, label I Branch <= rs1, rs2, label I Branch < (U) rs1, rs2, label I Branch > (U) rs1, rs2, label I Branch >= (U) rs1, rs2, label I Branch <= (U) rs1, rs2, label I NoOPeration - I Environment CALL -I Environment BREAK -I

Remarks

RISC-V instruction listings

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