The x86 instruction set has several times been extended with SIMD (Single instruction, multiple data) instruction set extensions. These extensions, starting from the MMX instruction set extension introduced with Pentium MMX in 1997, typically define sets of wide registers and instructions that subdivide these registers into fixed-size lanes and perform a computation for each lane in parallel.

Summary of SIMD extensions

The main SIMD instruction set extensions that have been introduced for x86 are:

SIMD instruction set extension Year Description Added in 1997 A set of 57 integer SIMD instruction acting on 64-bit vectors, mostly providing 8/16/32-bit lane-width operations.

Repurposed the old x87 FPU register-file as a bank of eight 64-bit vector registers, referred to as MM0..MM7 when used for MMX instructions. AMD K6,Intel Pentium II,Rise mP6,IDT WinChip C6,Transmeta Crusoe,DM&P Vortex86MX 1999 "Katmai New Instructions" - introduced a set of 70 new instructions. Most but not all of these instructions provide scalar and vector operations on 32-bit floating-point values in 128-bit SIMD vector registers. (Some of the SSE instructions were instead new MMX instructions and non-SIMD instructions such as SFENCE - the subset of SSE that excludes the 128-bit SIMD register instructions is known as "MMX+", and is supported on some AMD processors that didn't implement full SSE, notably early Athlons and Geode LX.)

SSE introduced a new set of eight vector registers XMM0..XMM7, each 128 bits, and a status/control register MXCSR.

This set of eight vector registers would later be extended to 16 registers with the introduction of x86-64. Intel Pentium III,AMD Athlon XP,VIA C3 "Nehemiah",Transmeta Efficeon 2000 Extended SSE with 144 new instructions - mainly additional instructions to work on scalars and vectors of 64-bit floating-point values, as well as 128-bit-vector forms of most of the MMX integer instructions. Intel Pentium 4,Intel Pentium M,AMD Athlon 64,Transmeta Efficeon,VIA C7 2004 "Prescott New Instructions": added a set of 13 new instructions, mostly horizontal add/subtract operations. Intel Pentium 4 "Prescott",Transmeta Efficeon 8800,AMD Athlon 64 "Venice",VIA C7,Intel Core "Yonah" 2006 Added a set of 32 new instructions to extend MMX and SSE, including a byte-shuffle instruction. Intel Core 2 "Conroe"/"Merom",VIA Nano 2000,Intel Atom "Bonnell",AMD "Bobcat",AMD FX "Bulldozer" 2007 AMD-only extension that added a set of 4 instructions, including bitfield insert/extract and scalar non-temporal store instructions. AMD K10 2007 Added a set of 47 instructions, including variants of integer min/max, widening integer conversions, vector lane insert/extract, and dot-product instructions. Intel Core 2 "Penryn",VIA Nano 3000,AMD FX "Bulldozer",AMD "Jaguar",Intel Atom "Silvermont",Zhaoxin ZX-A 2008 Added a set of 7 instructions, mostly pertaining to string processing. Intel Core i7 "Nehalem",AMD FX "Bulldozer",AMD "Jaguar",Intel Atom "Silvermont",VIA Nano QuadCore C4000,Zhaoxin ZX-C "ZhangJiang" 2011 Extended the XMM0..XMM15 vector registers to 256-bit registers, referred to as YMM0..YMM15 when used as full 256-bit registers.

Added three-operand variants of most of the SSE1-4 vector instructions, as well as 256-bit vector variants of most of the SSE1-4 vector instructions acting on 32/64-bit floating-point values. These new instruction variants are all encoded with the new VEX prefix. Intel Core i7 "Sandy Bridge",AMD FX "Bulldozer",AMD "Jaguar",VIA Nano QuadCore C4000,Zhaoxin ZX-C "ZhangJiang",Intel Atom "Gracemont" 2013 Added three-operand floating-point fused-multiply add operations, scalar and vector variants. Intel Core i7 "Haswell",AMD FX "Piledriver",Intel Atom "Gracemont",Zhaoxin KH-40000 "YongFeng" 2013 Added 256-bit vector variants of most of the MMX/SSE1-4 vector integer instructions. Also adds vector gather instructions. Intel Core i7 "Haswell",AMD FX "Excavator",VIA Nano QuadCore C4000,Intel Atom "Gracemont",Zhaoxin KH-40000 "YongFeng" 2016 Extended the YMM0..YMM15 vector registers to a set of 32 registers, each 512-bits wide - referred to as ZMM0..ZMM31 when used as 512-bit registers. Also added eight opmask registers K0..K7.

Added 512-bit versions of most of the MMX/SSE/AVX vector instructions, as well as a substantial number of additional instructions. These are mostly encoded with the new EVEX prefix (except for opmask management instructions, which continue to use the VEX prefix.)

Added the ability to perform per-vector-lane masking of the operation of most of its vector instructions, by using the opmask registers. Also added embedded rounding controls for floating-point instructions and a scalar-to-vector broadcast function for most instructions that can accept memory operands.

(See AVX-512#New instructions by sets for additional subsets.) 2023 Added a set of eight new tile registers, referred to as TMM0..TMM7. Each of these tile registers has a size of 8192 bits (16 rows of 64 bytes each). Also added a 64-byte tile configuration register TILECFG, and instructions to perform matrix multiplication on the tile registers with various data formats. 2024 Reformulation of AVX-512 that includes most of the optional AVX-512 subsets (F,CD,BW,DQ,VL,IFMA,VBMI,VNNI,BF16,VBMI2,BITALG,VPOPCNTDQ,FP16) as baseline functionality, and switches feature enumeration from the flag-based scheme of AVX-512 to a version-based scheme. No new instructions are added. Intel Xeon 6 "Granite Rapids" (2026) Adds instructions to convert to/from FP8 datatypes, perform arithmetic on BF16 numbers, saturating conversions from floating-point to integer, IEEE754-compliant min/max, and a few other instructions. (Intel Diamond Rapids)

MMX instructions and extended variants thereof

These instructions are, unless otherwise noted, available in the following forms: MMX: 64-bit vectors, operating on mm0..mm7 registers (aliased on top of the old x87 register file) SSE2: 128-bit vectors, operating on xmm0..xmm15 registers (xmm0..xmm7 in 32-bit mode) AVX: 128-bit vectors, operating on xmm0..xmm15 registers, with a new three-operand encoding enabled by the new VEX prefix. (AVX introduced 256-bit vector registers, but the full width of these vectors was in general not made available for integer SIMD instructions until AVX2.) AVX2: 256-bit vectors, operating on ymm0..ymm15 registers (extended versions of the xmm0..xmm15 registers) AVX-512: 512-bit vectors, operating on zmm0..zmm31 registers (zmm0..zmm15 are extended versions of the ymm0..ymm15 registers, while zmm16..zmm31 are new to AVX-512). AVX-512 also introduces opmasks, allowing the operation of most instructions to be masked on a per-lane basis by an opmask register (the lane width varies from one instruction to another). AVX-512 also adds broadcast functionality for many of its instructions - this is used with memory source arguments to replicate a single value to all lanes of a vector calculation. The tables below provide indications of whether opmasks and broadcasts are supported for each instruction, and if so, what lane-widths they are using.

For many of the instruction mnemonics, (V) is used to indicate that the instruction mnemonic exists in forms with and without a leading V - the form with the leading V is used for the VEX/EVEX-prefixed instruction variants introduced by AVX/AVX2/AVX-512, while the form without the leading V is used for legacy MMX/SSE encodings without VEX/EVEX-prefix.

Original Pentium MMX instructions, and SSE2/AVX/AVX-512 extended variants thereof

Description Instruction mnemonics Basic opcode MMX(no prefix) SSE2(66h prefix) AVX(VEX.66 prefix) AVX-512 (EVEX.66 prefix) supported subset lane bcst Empty MMX technology state.

Mark all the FP/MMX registers as Empty, so that they can be freely used by later x87 code. EMMS (MMX) 0F 77 Move scalar value from GPR (general-purpose register) or memory to vector register, with zero-fill 32-bit (V)MOVD mm, r/m32 0F 6E /r F 64-bit(x86-64) (V)MOVQ mm, r/m64,MOVD mm, r/m64 F Move scalar value from vector register to GPR or memory 32-bit (V)MOVD r/m32, mm 0F 7E /r F 64-bit(x86-64) (V)MOVQ r/m64, mm,MOVD r/m64, mm F Vector move between vector register and either memory or another vector register.

For move to/from memory, the memory address is required to be aligned for (V)MOVDQA variants but not for MOVQ.

The 128-bit VEX-encoded forms of VMOVDQA with a memory argument will, if the memory is cacheable, perform their memory accesses atomically. (MMX) 0F 7F /r rowspan=2 rowspan=2 rowspan=2 F 32 F 64 MOVQ mm, mm/m64(MMX)(V)MOVDQA xmm,xmm/m128 0F 6F /r rowspan=2 rowspan=2 rowspan=2 F 32 F 64 Pack 32-bit signed integers to 16-bit, with saturation 0F 6B /r BW1632 Pack 16-bit signed integers to 8-bit, with saturation (V)PACKSSWB mm, mm/m64 0F 63 /r BW8 Pack 16-bit unsigned integers to 8-bit, with saturation (V)PACKUSWB mm, mm/m64 0F 67 /r BW8 Unpack and interleave packed integers from the high halves of two input vectors 8-bit 0F 68 /r BW8 16-bit 0F 69 /r BW16 0F 6A /r F3232 Unpack and interleave packed integers from the low halves of two input vectors 8-bit 0F 60 /r BW8 16-bit 0F 61 /r BW16 32-bit 0F 62 /r F3232 Add packed integers 8-bit (V)PADDB mm, mm/m64 0F FC /r BW8 16-bit (V)PADDW mm, mm/m64 0F FD /r BW16 32-bit (V)PADDD mm, mm/m64 0F FE /r F3232 Add packed signed integers with saturation 8-bit (V)PADDSB mm, mm/m64 0F EC /r BW8 16-bit (V)PADDSW mm, mm/m64 0F ED /r BW16 Add packed unsigned integers with saturation 8-bit (V)PADDUSB mm, mm/m64 0F DC /r BW8 16-bit (V)PADDUSW mm, mm/m64 0F DD /r BW16 Subtract packed integers 8-bit (V)PSUBB mm, mm/m64 0F F8 /r BW8 16-bit (V)PSUBW mm, mm/m64 0F F9 /r BW16 32-bit (V)PSUBD mm, mm/m64 0F FA /r F3232 Subtract packed signed integers with saturation 8-bit (V)PSUBSB mm, mm/m64 0F E8 /r BW8 16-bit (V)PSUBSW mm, mm/m64 0F E9 /r BW16 Subtract packed unsigned integers with saturation 8-bit (V)PSUBUSB mm, mm/m64 0F D8 /r BW8 16-bit (V)PSUBUSW mm, mm/m64 0F D9 /r BW16 Compare packed integers for equality 8-bit (V)PCMPEQB mm, mm/m64 0F 74 /r BW8 16-bit (V)PCMPEQW mm, mm/m64 0F 75 /r BW16 32-bit (V)PCMPEQD mm, mm/m64 0F 76 /r F3232 Compare packed integers for signed greater-than 8-bit (V)PCMPGTB mm, mm/m64 0F 64 /r BW8 16-bit (V)PCMPGTW mm, mm/m64 0F 65 /r BW16 32-bit (V)PCMPGTD mm, mm/m64 0F 66 /r F3232 Multiply packed 16-bit signed integers, add results pairwise into 32-bit integers (V)PMADDWD mm, mm/m64 0F F5 /r BW32 Multiply packed 16-bit signed integers, store high 16 bits of results (V)PMULHW mm, mm/m64 0F E5 /r BW16 Multiply packed 16-bit integers, store low 16 bits of results (V)PMULLW mm, mm/m64 0F D5 /r BW16 Vector bitwise AND (V)PAND mm, mm/m64 0F DB /r rowspan=2 rowspan=2 rowspan=2 F 32 32 F 64 64 Vector bitwise AND-NOT (V)PANDN mm, mm/m64 0F DF /r rowspan=2 rowspan=2 rowspan=2 F 32 32 F 64 64 Vector bitwise OR (V)POR mm, mm/m64 0F EB /r rowspan=2 rowspan=2 rowspan=2 F 32 32 F 64 64 Vector bitwise XOR (V)PXOR mm, mm/m64 0F EE /r rowspan=2 rowspan=2 rowspan=2 F 32 32 F 64 64 Left-shift of packed integers, with common shift-amount 16-bit (V)PSLLW mm, imm8 0F 71 /6 ib BW16 (V)PSLLW mm, mm/m64 0F F1 /r BW16 32-bit (V)PSLLD mm, imm8 F3232 (V)PSLLD mm, mm/m64 0F F2 /r F32 64-bit (V)PSLLQ mm, imm8 F6464 (V)PSLLQ mm, mm/m64 0F F3 /r F64 Right-shift of packed signed integers, with common shift-amount 16-bit (V)PSRAW mm, imm8 0F 71 /4 ib BW16 (V)PSRAW mm, mm/m64 0F E1 /r BW16 32-bit (V)PSRAD mm, imm8 0F 72 /4 ib F3232 (V)PSRAD mm, mm/m64 0F E2 /r F32 Right-shift of packed unsigned integers, with common shift-amount 16-bit (V)PSRLW mm, imm8 0F 71 /2 ib BW16 (V)PSRLW mm, mm/m64 0F D1 /r BW16 32-bit (V)PSRLD mm, imm8 0F 72 /2 ib F3232 (V)PSRLD mm, mm/m64 0F D2 /r F32 (V)PSRLQ mm, imm8 0F 73 /2 ib F6464 (V)PSRLQ mm, mm/m64 0F D3 /r F64

MMX instructions added with MMX+/SSE/SSE2/SSSE3, and SSE2/AVX/AVX-512 extended variants thereof