In computing, channel I/O is a high-performance input/output (I/O) architecture that is implemented in various forms on a number of computer architectures, especially on mainframe computers. In the past, channels were generally implemented with custom devices, variously named channel, I/O processor, I/O controller, I/O synchronizer, or DMA controller.
Overview Many I/O tasks can be complex and require logic to be applied to the data to convert formats and other similar duties. In these situations, the simplest solution is to ask the CPU to handle the logic, but because I/O devices are relatively slow, a CPU could waste time waiting for the data from the device. This situation is called 'I/O bound'.
Channel architecture avoids this problem by processing some or all of the I/O task without the aid of the CPU by offloading the work to dedicated logic. Channels are logically self-contained, with sufficient logic and working storage to handle I/O tasks. Some are powerful or flexible enough to be used as a computer on their own and can be as a form of coprocessor, for example, the 7909 Data Channel on an IBM 7090 or IBM 7094; however, most are not. On some systems the channels use memory or registers addressable by the central processor as their working storage, while on other systems it is present in the channel hardware. Typically, there are standard interfaces between channels and external peripheral devices, and multiple channels can operate concurrently.
A CPU typically designates a block of storage as, or sends, a relatively small channel program to the channel in order to handle I/O tasks, which the channel and controller can, in many cases, complete without further intervention from the CPU (exception: those channel programs which utilize 'program controlled interrupts', PCIs, to facilitate program loading, demand paging and other essential system tasks).
When I/O transfer is complete or an error is detected, the controller typically communicates with the CPU through the channel using an interrupt. Since the channel normally has direct access to the main memory, it is also often referred to as a direct memory access (DMA) controller.
In the most recent implementations, the channel program is initiated and the channel processor performs all required processing until either an ending condition or a program controlled interrupt (PCI). This eliminates much of the CPU-Channel interaction and greatly improves overall system performance. The channel may report several different types of ending conditions, which may be unambiguously normal, may unambiguously indicate an error or whose meaning may depend on the context and the results of a subsequent sense operation. In some systems an I/O controller can request an automatic retry of some operations without CPU intervention. In earlier implementations, any error, no matter how small, required CPU intervention, and the overhead was, consequently, much higher. A program-controlled interruption (PCI) is still used by certain legacy operations, but the trend is to move away from such PCIs, except where unavoidable.
History The first use of channel I/O was with the IBM 709 vacuum tube mainframe in 1957, whose Model 766 Data Synchronizer was the first channel controller. The 709's transistorized successor, the IBM 7090, had two to eight 6-bit channels (the 7607) and a channel multiplexor (the 7606) which could control up to eight channels. The 7090 and 7094 could also have up to eight 8-bit channels with the 7909.
While IBM used data channel commands on some of its computers, and allowed command chaining on, e.g., the 7090, most other vendors used channels that dealt with single records. However, some systems, e.g., GE-600 series, had more sophisticated I/O architectures.
Later, the IBM System/360 and System/370 families of computer offered channel I/O on all models. For the lower-end System/360 Models 50 and below and System/370 Model 158 and below, channels are implemented in microcode on the CPU, and the CPU itself operates in one of two modes, either "CPU Mode" or "Channel Mode", with the channel mode 'stealing' cycles from the CPU mode. For larger IBM System/360 and System/370 computers the channels were still bulky and expensive separate components, such as the IBM 2860 Selector channel (one to three selector channels in a single box), the IBM 2870 Byte multiplexor channel (one multiplexer channel, and, optionally, one to four selector subchannels in a single box), and the IBM 2880 Block multiplexor channel (one or two block multiplexor channels in a single box). On the 303x processor complexes, the channels are implemented in independent channel directors in the same cabinet as the CPU, with each channel director implementing a group of channels.
Much later, the channels were implemented as an on-board processor residing in the same box as the CPU, generally referred to as a "channel processor", and which was usually a RISC processor, but which could be a System/390 microprocessor with special microcode as in IBM's CMOS mainframes.
Amdahl refinements Amdahl Corporation's hardware implementation of System/370 compatible channels was quite different. A single internal unit, called the "C-Unit", supported up to sixteen channels using the very same hardware for all supported channels. Two internal "C-Units" were possible, supporting up to 32 total channels. Each "C-Unit" independently performed a process generally called a "shifting channel state processor" (a type of barrel processor), which implemented a specialized finite-state machine (FSM). Each CPU cycle, every 32 nanoseconds in the 470V/6 and /5 and every 26 nanoseconds in the 470V/7 and /8, the "C-unit" read the complete status of next channel in priority sequence and its I/O Channel in-tags. The necessary actions defined by that channel's last state and its in-tags were performed: data was read from or written to main storage, the operating system program was interrupted if such interruption was specified by the channel program's Program Control Interrupt flag, and the "C-Unit" finally stored that channel's next state and set its I/O Channel out-tags, and then went on to the next lower priority channel. Preemption was possible, in some instances.
Sufficient FIFO storage was provided within the "C-Unit" for all channels which were emulated by this FSM. Channels could be easily reconfigured to the customer's choice of selector, byte multiplexor, or block multiplexor channel, without any significant restrictions by using maintenance console commands. "Two-byte interface" was also supported as was "Data-In/Data-Out" and other high-performance IBM channel options.
Built-in channel-to-channel adapters were also offered, called CCAs in Amdahl-speak, but called CTCs or CTCAs in IBM-speak. A real game-changer, and this forced IBM to redesign its mainframes to provide similar channel capability and flexibility. IBM's initial response was to include stripped-down Model 158s, operating in "Channel Mode" only, as the Model 303x channel units. In the Amdahl "C-unit" any channel could be any type, selector, byte multiplexor, or block multiplexor, without reserving channels 0 and 4 for the byte multiplexers, as on some IBM models.
Other implementations Some of the earliest commercial non-IBM channel systems were on the UNIVAC 490, CDC 1604, Burroughs B5000, UNIVAC 1107, and GE 635. Since then, channel controllers have been a standard part of most mainframe designs, and still remain a primary feature of mainframes when compared to smaller personal computers and network computing.
The 1965 CDC 6600 supercomputer utilized 10 logically independent computers called peripheral processors (PPs) and 12 simple I/O channels for this role. PPs were a modified version of CDC's first personal computers, the 12-bit CDC 160 and 160A. The operating system initially resided and executed in PP0. The channels had no direct access to memory and could not cause interrupts; software on a PP used synchronous instructions to transfer data between the channel and either the A register or PP memory.
SCSI was introduced in 1981 as a low cost channel equivalent to the IBM Block Multiplexer Channel, and later became widespread in the form of the Fibre Channel Protocol and Serial Attached SCSI.
Modern computers may have channels in the form of bus mastering peripheral devices, such as PCI direct memory access (DMA) devices. The rationale for these devices is the same as for the original channel controllers, namely off-loading of transfer, interrupts, and context switching tasks from the main CPU.
Channel controllers have been made as small as single-chip designs with multiple channels on them, used in the NeXT computers for instance.
Description On large mainframe computer systems, CPUs are only one of several hardware components that work in parallel. Channels are independent hardware components that coordinate all input from and output to a set of special I/O controllers (the exact names of which vary from one manufacturer to another) or devices. There may be several CPUs and channels. The overall architecture optimizes input/output performance without degrading pure CPU performance. Since most real-world applications of mainframe systems are heavily I/O-intensive business applications, this architecture helps provide the very high levels of throughput that distinguish mainframes from other types of computers.
The CPU machine instructions for input and output of a system that uses channel I/O are used to pass input/output commands to the specialized I/O hardware in the form of channel programs. I/O thereafter proceeds without intervention from the CPU until an event requiring notification of the operating system occurs, at which point the I/O hardware signals an interrupt to the CPU.
In some lower-end systems, such as lower-end System/360 and some lower-end System/370 mainframes, the channel I/O operations were implemented using CPU data paths and microcode; this allowed software to run on machines with independent channels and on machines with CPU-based channels without change.
A channel is not merely a medium of communication, despite the name; it is a programmable device that handles all details of I/O after being given a list of I/O operations to carry out (the channel program).
Each channel may support one or more controllers and/or devices, but each channel program may only be directed at one of those connected devices. A channel program contains lists of commands to the channel itself and to the controller and device to which it is directed. Once the operating system has prepared a complete list of channel commands, it executes a single I/O machine instruction to initiate the channel program; the channel thereafter assumes control of the I/O operations until they are completed.
It is possible to develop very complex channel programs, including testing of data and conditional branching within that channel program. This flexibility frees the CPU from the overhead of starting, monitoring, and managing individual I/O operations. The specialized channel hardware, in turn, is dedicated to I/O and can carry it out more efficiently than the CPU (and entirely in parallel with the CPU). Channel I/O is not unlike the Direct Memory Access (DMA) of microcomputers, only more complex and advanced.
The best-known implementation of channel I/O is that of the IBM System/360 family of mainframes and its successors, but similar implementations have been adopted by IBM on earlier lines of computers, e.g., 1410 and 7010, 7030, and by other mainframe vendors, such as Control Data, Bull (General Electric/Honeywell) and Unisys.