The Intel Core microarchitecture (provisionally referred to as Next Generation Micro-architecture, Note that all mentions of "Next-Generation Micro-architecture" in Intel's slides have asterisks that warn that "micro-architecture name TBD". and developed as Merom) is a multi-core processor microarchitecture launched by Intel in mid-2006. It is a refreshed successor to the Enhanced Pentium M, the previous iteration of the P6 microarchitecture series which started in 1995 with Pentium Pro. It also replaced the NetBurst microarchitecture, which suffered from high power consumption and heat intensity due to an inefficient pipeline designed for high clock rate. In early 2004, Prescott needed very high power to reach the clocks it needed for competitive performance, making it unsuitable for the shift to dual/multi-core CPUs. On May 7, 2004, Intel confirmed the cancellation of the next NetBurst, Tejas and Jayhawk. Intel had been developing Merom, the 64-bit evolution of the Pentium M, since 2001, and decided to expand it to all market segments, replacing NetBurst in desktop computers and servers. It inherited from Pentium M the choice of a short and efficient pipeline, delivering superior performance despite not reaching the high clocks of NetBurst.
The first processors that used this architecture were code-named 'Merom', 'Conroe', and 'Woodcrest'; Merom is for mobile computing, Conroe is for desktop systems, and Woodcrest is for servers and workstations. While architecturally identical, the three processor lines differ in the socket used, bus speed, and power consumption. The first Core-based desktop and mobile processors were branded Core 2, later expanding to the lower-end Pentium Dual-Core, Pentium and Celeron brands; while server and workstation Core-based processors were branded Xeon.
Features
The Core microarchitecture returned to lower clock rates and improved the use of both available clock cycles and power when compared with the preceding NetBurst microarchitecture of the Pentium 4 and D-branded CPUs. The Core microarchitecture provides more efficient decoding stages, execution units, caches, and buses, reducing the power consumption of Core 2-branded CPUs while increasing their processing capacity. Intel's CPUs have varied widely in power consumption according to clock rate, architecture, and semiconductor process, shown in the CPU power dissipation tables.
Like the last NetBurst CPUs, Core based processors feature multiple cores and hardware virtualization support (marketed as Intel VT-x), and Intel 64 and SSSE3. However, Core-based processors do not have the hyper-threading technology as in Pentium 4 processors.
The L1 cache of the Core microarchitecture at 64 KB L1 cache/core (32 KB L1 Data + 32 KB L1 Instruction) is as large as in Pentium M, up from 32 KB on Pentium II / III (16 KB L1 Data + 16 KB L1 Instruction). The consumer version also lacks an L3 cache as in the Gallatin core of the Pentium 4 Extreme Edition, though it is exclusively present in high-end versions of Core-based Xeons.
Processors using the follow-on Nehalem microarchitecture include hyper-threading, and consumer parts once again have an L3 cache.
Roadmap
Technology
While the Core microarchitecture is a major architectural revision, it is based in part on the Pentium M processor family designed by Intel Israel. The pipeline of Core/Penryn is 14 stages long – less than half of Prescott's. Penryn's successor Nehalem has a two cycles higher branch misprediction penalty than Core/Penryn. Core can ideally sustain up to 4 instructions per cycle (IPC) execution rate, compared to the 3 IPC capability of P6, Pentium M and NetBurst microarchitectures. The new architecture is a dual core design with a shared L2 cache engineered for maximum performance per watt and improved scalability.
One new technology included in the design is Macro-Ops Fusion, which combines two x86 instructions into a single micro-operation. For example, a common code sequence like a compare followed by a conditional jump would become a single micro-op. However, this technology does not work in 64-bit mode.
Core can speculatively execute loads ahead of preceding stores with unknown addresses.
Other new technologies include 1 cycle throughput (2 cycles previously) of all 128-bit SSE instructions and a new power saving design. All components will run at minimum speed, raising speed dynamically as needed (similar to AMD's Cool'n'Quiet power-saving technology, and Intel's own SpeedStep technology from earlier mobile processors). This allows the chip to produce less heat, and minimize power use.
For most Woodcrest CPUs, the front-side bus (FSB) runs at 1333 MT/s; however, this is scaled down to 1066 MT/s for lower end 1.60 and 1.86 GHz variants. The Merom mobile variant was initially targeted to run at an FSB of 667 MT/s while the second wave of Meroms, supporting 800 MT/s FSB, were released as part of the Santa Rosa platform with a different socket in May 2007. The desktop-oriented Conroe began with models having an FSB of 800 MT/s or 1066 MT/s with a 1333 MT/s line officially launched on July 22, 2007.
The power use of these processors is very low: average energy use is to be in the 1–2 watt range in ultra-low voltage variants, with thermal design powers (TDPs) of 65 watts for Conroe and most Woodcrests, 80 watts for the 3.0 GHz Woodcrest, and 40 or 35 watts for the low-voltage Woodcrest. In comparison, a 2.2 GHz AMD Opteron 875HE processor consumes 55 watts, while the energy efficient Socket AM2 line fits in the 35 watt thermal envelope (specified a different way so not directly comparable). Merom, the mobile variant, is listed at 35 watts TDP for standard versions and 5 watts TDP for ultra-low voltage (ULV) versions.
Previously, Intel announced that it would now focus on power efficiency, rather than raw performance. However, at Intel Developer Forum (IDF) in spring 2006, Intel advertised both. Some of the promised numbers were: 20% more performance for Merom at the same power level; compared to Core Duo 40% more performance for Conroe at 40% less power; compared to Pentium D 80% more performance for Woodcrest at 35% less power; compared to the original dual-core Xeon
Processor cores
The processors of the Core microarchitecture can be categorized by number of cores, cache size, and socket; each combination of these has a unique code name and product code that is used across several brands. For instance, code name "Allendale" with product code 80557 has two cores, 2 MB L2 cache and uses the desktop socket 775, but has been marketed as Celeron, Pentium, Core 2, and Xeon, each with different sets of features enabled. Most of the mobile and desktop processors come in two variants that differ in the size of the L2 cache, but the specific amount of L2 cache in a product can also be reduced by disabling parts at production time. Tigerton dual-cores and all quad-core processors except - are multi-chip modules combining two dies. For the 65 nm processors, the same product code can be shared by processors with different dies, but the specific information about which one is used can be derived from the stepping.
Cores Mobile Desktop, UP Server CL Server DP Server MP ServerSingle-Core 65 nm 1 Merom-L80537 Conroe-L80557 Single-Core 45 nm Penryn-L80585 Wolfdale-CL80588 Dual-Core 65 nm 2 Merom-2M80537 Merom80537 Allendale80557 Conroe80557 Conroe-CL80556 Woodcrest80556 Tigerton80564Dual-Core 45 nm Penryn-3M80577 Penryn80576 Wolfdale-3M80571 Wolfdale80570 Wolfdale-CL80588 Wolfdale-DP80573 Quad-Core 65 nm 4 Kentsfield80562 Clovertown80563 Tigerton QC80565Quad-Core 45 nm Penryn-QC80581 Yorkfield-6M80580 Yorkfield80569 Yorkfield-CL80584 Harpertown80574 Dunnington QC80583Six-Core 45 nm 6 Dunnington80582
Conroe/Merom (65 nm)
The original Core 2 processors are based on the same dies that can be identified as CPUID Family 6 Model 15. Depending on their configuration and packaging, their code names are Conroe (LGA 775, 4 MB L2 cache), Allendale (LGA 775, 2 MB L2 cache), Merom (Socket M, 4 MB L2 cache) and Kentsfield (multi-chip module, LGA 775, 2x4MB L2 cache). Merom and Allendale processors with limited features are in Pentium Dual Core and Celeron processors, while Conroe, Allendale and Kentsfield also are sold as Xeon processors.
Additional code names for processors based on this model are Woodcrest (LGA 771, 4 MB L2 cache), Clovertown (MCM, LGA 771, 2×4MB L2 cache) and Tigerton (MCM, Socket 604, 2×4MB L2 cache), all of which are marketed only under the Xeon brand.
Processor Brand name Model (list) Cores L2 Cache Socket TDPMobile processors Merom-2MMobile Core 2 Duo U7xxx 2 2 MB BGA479 10 W Merom L7xxx 4 MB 17 W MeromMerom-2M T5xxxT7xxx 2–4 MB Socket MSocket PBGA479 35 W Merom XE Mobile Core 2 Extreme X7xxx 2 4 MB Socket P 44 W MeromCeleron M 5x0 1 1 MB Socket MSocket P 30 W Merom-2M 5x5 Socket P 31 W Merom-2M Celeron Dual-Core T1xxx 2 512–1024 KB 35 W Merom-2M Pentium Dual-Core T2xxxT3xxx 2 1 MB 35 WDesktop processors Allendale Xeon 3xxx 2 2 MB LGA 775 65 W Conroe 3xxx 2–4 MBConroe andAllendaleCore 2 Duo E4xxx 2 2 MB LGA 775 65 W E6xx0 2–4 MB Conroe-CL E6xx5 2–4 MB LGA 771 Conroe-XE Core 2 Extreme X6xxx 2 4 MB LGA 775 75 W Allendale Pentium Dual-Core E2xxx 2 1 MB 65 W Allendale Celeron E1xxx 2 512 KB 65 W Kentsfield Xeon 32xx 4 2×4 MB 95–105 W Kentsfield Core 2 Quad Q6xxx 4 2×4 MB 95–105 W Kentsfield XE Core 2 Extreme QX6xxx 4 2×4 MB 130 W Woodcrest Xeon 51xx 2 4 MB LGA 771 65–80 WClovertown L53xx 4 2×4 MB LGA 771 40–50 W E53xx 80 W X53xx 120–150 W Tigerton E72xx 2 2×4 MB Socket 604 80 WTigerton QC L73xx 4 50 W E73xx 2×2–2×4 MB 80 W X73xx 2×4 MB 130 W
Conroe-L/Merom-L
The Conroe-L and Merom-L processors are based around the same core as Conroe and Merom, but only contain a single core and 1 MB of L2 cache, significantly reducing production cost and power consumption of the processor at the expense of performance compared to the dual-core version. It is used only in ultra-low voltage Core 2 Solo U2xxx and in Celeron processors and is identified as CPUID family 6 model 22.
Processor Brand name Model (list) Cores L2 Cache Socket TDP Merom-L Mobile Core 2 Solo U2xxx 1 2 MB BGA479 5.5 W Merom-LCeleron M 5x0 1 512 KB Socket MSocket P 27 W Merom-L 5x3 512–1024 KB BGA479 5.5–10 W Conroe-LCeleron M 4x0 1 512 KB LGA 775 35 W Conroe-CL 4x5 LGA 771 65 W
Penryn/Wolfdale (45 nm)
In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn (Socket P), Wolfdale (LGA 775) and Yorkfield (MCM, LGA 775), some of which are also sold as Celeron, Pentium and Xeon processors. In the Xeon brand, the Wolfdale-DP and Harpertown code names are used for LGA 771 based MCMs with two or four active Wolfdale cores.
Architecturally, 45 nm Core 2 processors feature SSE4.1 and new divide/shuffle engine.
The chips come in two sizes, with 6 MB and 3 MB L2 cache. The smaller version is commonly called Penryn-3M and Wolfdale-3M and Yorkfield-6M, respectively. The single-core version of Penryn, listed as Penryn-L here, is not a separate model like Merom-L but a version of the Penryn-3M model with only one active core.