The ARM Cortex-A520 is a CPU microarchitecture designed by Arm Holdings and licensed as a semiconductor intellectual property core. It implements the 64-bit ARMv9 instruction set and supports heterogeneous computing via a big.LITTLE configuration. The design succeeds the Cortex-A510 in its role as a low performance, power efficient core, and is announced in 2023 together with the Cortex-A720 and the X4.
Technical overview The A520 is an in-order CPU core intended for low-performance, low-power workloads. ARMv9.2 instruction set Claimed performance improvement of up to 8% over the Cortex-A510 Support only Aarch64 applications Optional L2 cache of up to 512KiB per core Supports QARMA3 pointer authentication codes (PAC)
Architecture comparison
"LITTLE" core
uArchCortex-A53Cortex-A55Cortex-A510Cortex-A520 Codename Apollo Ananke Klein HayesPeak clock speed~2 GHzArchitectureARMv8.0-AARMv8.2-AARMv9.0-AARMv9.2-AAArch32-bit and 64-bit 64-bit Branch predictor history (entries)3072 -Out-of-order executionNoL0 CacheNoL1-I + L1-D8/64+8/64 KiB16/64+16/64 KiB32/64+32/64 KiBL20–256 KiB0–512 KiBL3None0–4 MiB0–16 MiB0–32 MiBDecode Width233 (2 ALU)Dispatch8
See also ARM Cortex-X4, related high performance microarchitecture ARM Cortex-A720, related efficient sustained performance microarchitecture Comparison of ARMv8-A cores, ARMv8 family
References