Paul Richman (born November 17, 1942) is an American semiconductor physicist and author.
Education In 1963, Richman studied at M.I.T. and graduated with a Bachelor of Science in electrical engineering. In 1964, he earned a Master of Science in electrical engineering from Columbia University.
Career In 1971, Richman co-founded Standard Microsystems Corp (SMSC) as a research and development firm. Before co-founding SMSC, he worked as a semiconductor physicist at General Telephone and Electronics. In 1987, he moved to Japan with his family and started a collaboration called Standard Microsystems Japan. Between 1971 and 1999, he served as the chief executive officer, president and chairman of Standard Microsystems. During his tenure, SMSC became the largest chip maker on Long Island, and Intel Corp acquired a stake in the company. Newsday has called him a pioneer in the computer chip industry. He introduced a method for decreasing the size of chips by moving transistors closer together while increasing operating speeds and as a result devices operate quickly and efficiently.
As an academic, Richman served as a visiting professor of electrical engineering at the City University of New York between 1974 and 1975 and at the State University of New York at Stony Brook between 1975 and 1987.
From 1998 to 2002, he served on the Massachusetts Institute of Technology's Visiting Committee for Electrical Engineering and Computer Science.
Richman developed and held the basic patent for COPLAMOS technology, which pioneered the use of field-doped, locally-oxidized structures in metal–oxide–semiconductor (M.O.S.) integrated circuits.
Awards
1978: Annual Achievement Award from Electronics (magazine) for his contributions to the development of microchips.
1982: Elected a Fellow of the Institute of Electrical and Electronics Engineers, the IEEE.
1998: IEEE's Harold A. Wheeler Award.
2000: IEEE's Third Millennium medal.
2012: Elected to the Long Island Technology Hall of Fame.
Patents
Complementary Enhancement Type MOS Transistors. Method for Manufacturing Metal-Oxide Silicon Devices. Method for Selectively Establishing Regions of Different Surface Charge Densities in a Silicon Wafer. Method for Selectively Establishing Regions of Different Surface Charge Densities in a Silicon Wafer. USPTO Method of Modifying Electrical Characteristics of MOS Devices Using Ion Implantation.Method of Modifying Electrical Characteristics of MOS Devices Using Ion Implantation. USPTO Semiconductor Integrated Circuit Structure with Selectively Modified Insulation Layer.Semiconductor Integrated Circuit Structure with Selectively Modified Insulation Layer. USPTO Hermetic plastic dual-in-line package for a semiconductor integrated circuit.Hermetic plastic dual-in-line package for a semiconductor integrated circuit. USPTO Solid State Field Effect Device.Solid State Field Effect Device. USPTO Insulated-gate Field Effect Transistors Utilizing a High Resistivity Substrate.Insulated-gate Field Effect Transistors Utilizing a High Resistivity Substrate. USPTO MOS Field-effect Transistor Structure with Mesa-like Contact and Gate Areas and Selectively Deeper Junctions.MOS Field-effect Transistor Structure with Mesa-like Contact and Gate Areas and Selectively Deeper Junctions. USPTO Bipolar MOS Field Effect Transistor.Bipolar MOS Field Effect Transistor. USPTO MOS Integrated Circuit with Substrate Containing Selectively Formed Resistivity Regions.MOS Integrated Circuit with Substrate Containing Selectively Formed Resistivity Regions. USPTO Method of Fabricating High Density Refractory Metal Gate MOS Integrated Circuits Utilizing the Gate as a Selective Diffusion and Oxidation Mask.Method of Fabricating High Density Refractory Metal Gate MOS Integrated Circuits Utilizing the Gate as a Selective Diffusion and Oxidation Mask. USPTO Integrated MOS circuit.Integrated MOS circuit. USPTO Method for Manufacturing a Composite Device, Of the Metal-oxide-semiconductor Type, Control Electrode with Low Superficial Resistivity, And Device Obtained.Method for Manufacturing a Composite Device, Of the Metal-oxide-semiconductor Type, Control Electrode with Low Superficial Resistivity, And Device Obtained. USPTO MOS Integrated Circuit Structure and Method for Its Fabrication.MOS Integrated Circuit Structure and Method for Its Fabrication. Google Patents
References