Instructions that have at some point been present as documented instructions in one or more x86 processors, but where the processor series containing the instructions are discontinued or superseded, with no known plans to reintroduce the instructions.

Intel instructions

i386 instructions

The following instructions were introduced in the Intel 80386, but later discontinued: Instruction Opcode Description Eventual fate Extract Bit String Discontinued from revision B1 of the 80386 onwards.

Opcodes briefly reused for CMPXCHG in Intel 486 stepping A only − CMPXCHG was moved to different opcode from 486 stepping B onwards.

Opcodes later reused for VIA PadLock. IBTS r/m, r 0F A7 /r Insert Bit String 0F 24 /r Move from test register Present in Intel 386 and 486 − not present in Intel Pentium or any later Intel CPUs (except they're present in the i486-derived Quark X1000).Present in all Cyrix CPUs. MOV TRx,r32 0F 26 /r Move to test register

Itanium instructions

These instructions are only present in the x86 operation mode of early Intel Itanium processors with hardware support for x86. This support was added in "Merced" and removed in "Montecito", replaced with software emulation. Instruction Opcode Description JMPE r/m16JMPE r/m32 NFx 0F 00 /6 Jump To Intel Itanium Instruction Set.Intel Itanium Architecture Software Developer's Manual, volume 4 , (document number: 323208, revision 2.3, May 2010).

MPX instructions

These instructions were introduced in 6th generation Intel Core "Skylake" CPUs. The last CPU generation to support them was the 9th generation Core "Coffee Lake" CPUs.

Intel MPX adds 4 new registers, BND0 to BND3, that each contains a pair of addresses. MPX also defines a bounds-table as a 2-level directory/table data structure in memory that contains sets of upper/lower bounds. Instruction Opcode Description BNDMK b, m Make lower and upper bound from memory address expression.

The lower bound is given by base component of address, the upper bound by 1's-complement of the address as a whole. BNDCL b, r/m F3 0F 1A /r Check address against lower bound.

BNDCL, BNDCU and BNDCL all produce a #BR exception if the bounds check fails. BNDCU b, r/m F2 0F 1A /r Check address against upper bound in 1's-complement form BNDCN b, r/m F2 0F 1B /r Check address against upper bound. 66 0F 1A /r Move a pair of memory bounds to/from memory or between bounds-registers. BNDMOV b/m, b BNDLDX b,mib NP 0F 1A /r Load bounds from the bounds-table, using address translation using an sib-addressing expression mib. BNDSTX mib,b NP 0F 1B /r Store bounds into the bounds-table, using address translation using an sib-addressing expression mib. BND F2 Instruction prefix used with certain branch instructions to indicate that they should not clear the bounds registers.

The XSAVE area that was used to save MPX registers on context switches has been repurposed for APX.

Hardware Lock Elision

The Hardware Lock Elision feature of Intel TSX is marked in the Intel SDM as removed from 2019 onwards.Intel SDM, volume 1 , order no. 253665-083, mar 2024, chapter 2.5 This feature took the form of two instruction prefixes, XACQUIRE and XRELEASE, that could be attached to memory atomics/stores to elide the memory locking that they represent.

Instruction prefix Opcode Description XACQUIRE F2 Instruction prefix to indicate start of hardware lock elision, used with memory atomic instructions only (for other instructions, the F2 prefix may have other meanings). When used with such instructions, may start a transaction instead of performing the memory atomic operation. XRELEASE F3 Instruction prefix to indicate end of hardware lock elision, used with memory atomic/store instructions only (for other instructions, the F3 prefix may have other meanings). When used with such instructions during hardware lock elision, will end the associated transaction instead of performing the store/atomic. The XACQUIRE and XRELEASE prefixes can be used with the following instructions: LOCK-prefixed memory read–modify–write forms of the instructions XCHG,ADD,ADC,SUB,SBB,AND,OR,XOR,INC,DEC,NEG,NOT,BTC,BTR,BTS,XADD,CMPXCHG and CMPXCHG8B. The memory read–modify–write form of the XCHG instruction, regardless of LOCK prefix. XRELEASE can also be used with some store instructions without LOCK prefix: MOV mem,reg (opcodes 88h/89h) and MOV mem,imm (opcodes C6h/C7h) These prefixes cannot be used with the CMPXCHG16B instruction, nor with the direct-offset store opcodes (opcodes A2h/A3h).

VP2INTERSECT instructions The VP2INTERSECT instructions (an AVX-512 subset) were introduced in Tiger Lake (11th generation mobile Core processors), but were never officially supported on any other Intel processors – they are now considered deprecatedR. Singhal, Yes. Deprecated. (about VP2INTERSECT), Jul 19, 2023. on Jul 23, 2023. and are listed in the Intel SDM as removed from 2023 onwards.

As of July 2024, the VP2INTERSECT instructions have been re-introduced on AMD Zen 5 processors.Alexander Yee, Zen5's AVX512 Teardown + More , 7 Aug 2024 Instruction Opcode Description VP2INTERSECTD k1+1, ymm2, ymm3/m256/m32bcstVP2INTERSECTD k1+1, zmm2, zmm3/m512/m32bcst Store, in an even/odd pair of mask registers, the indicators of the locations of value matches between 32-bit lanes in the two vector source arguments. VP2INTERSECTQ k1+1, ymm2, ymm3/m256/m64bcstVP2INTERSECTQ k1+1, zmm2, zmm3/m512/m64bcst Store, in an even/odd pair of mask registers, the indicators of the locations of value matches between 64-bit lanes in the two vector source arguments.

Instructions specific to Xeon Phi processors

"Knights Corner" instructions

The first generation Xeon Phi processors, codenamed "Knights Corner" (KNC), supported a large number of instructions that are not seen in any later x86 processor. An instruction reference is availableIntel, Intel® Xeon Phi™ Coprocessor Instruction Set Architecture Reference Manual, sep 2012, order no. 327364-001. Archived on 4 Aug 2021. − the instructions/opcodes unique to KNC are the ones with VEX and MVEX prefixes (except for the KMOV, KNOT and KORTEST instructions − these are kept with the same opcodes and function in AVX-512, but with an added "W" appended to their instruction names).

Most of these KNC-unique instructions are similar but not identical to instructions in AVX-512 − later Xeon Phi processors replaced these instructions with AVX-512.

Early versions of AVX-512 avoided the instruction encodings used by KNC's MVEX prefix, however with the introduction of Intel APX (Advanced Performance Extensions) in 2023, some of the old KNC MVEX instruction encodings have been reused for new APX encodings. For example, both KNC and APX accept the instruction encoding as valid, but assign different meanings to it: KNC: – vector load with data conversion APX: – vector load with one of the new APX extended-GPRs used as scaled index

"Knights Landing" and "Knights Mill" instructions

Some of the AVX-512 instructions in the Xeon Phi "Knights Landing" and later models belong to the AVX-512 subsets "AVX512ER", "AVX512_4FMAPS", "AVX512PF" and "AVX512_4VNNIW", all of which are unique to the Xeon Phi series of processors. The ER and PF subsets were introduced in "Knights Landing" − the 4FMAPS and 4VNNIW instructions were later added in "Knights Mill".

The ER and 4FMAPS instructions are floating-point arithmetic instructions that all follow a given pattern where: EVEX.W is used to specify floating-point format (0=FP32, 1=FP64) The bottom opcode bit is used to select between packed and scalar operation (0: packed, 1:scalar) For a given operation, all the scalar/packed variants belong to the same AVX-512 subset. The instructions all support result masking by opmask registers. The AVX512ER instructions also all support broadcast of memory operands. The only supported vector width is 512 bits.

Operation AVX-512subset Basic opcode FP32 instructions (W=0) FP64 instructions (W=1) RC/SAE Packed Scalar Packed Scalar Xeon Phi specific instructions (ER, 4FMAPS) Reciprocal approximation with an accuracy of ER SAE Reciprocal square root approximation with an accuracy of ER SAE Exponential approximation with relative error ER EVEX.66.0F38 C8 /r VEXP2PS z,z/m512 VEXP2PD z,z/m512 SAE Fused-multiply-add, 4 iterations 4FMAPS Fused negate-multiply-add, 4 iterations 4FMAPS

The AVX512PF instructions are a set of 16 prefetch instructions. These instructions all use VSIB encoding, where a memory addressing mode using the SIB byte is required, and where the index part of the SIB byte is taken to index into the AVX512 vector register file rather than the GPR register file. The selected AVX512 vector register is then interpreted as a vector of indexes, causing the standard x86 base+index+displacement address calculation to be performed for each vector lane, causing one associated memory operation (prefetches in case of the AVX512PF instructions) to be performed for each active lane. The instruction encodings all follow a pattern where: EVEX.W is used to specify format of the prefetchable data (0:FP32, 1:FP64) The bottom bit of the opcode is used to indicate whether the AVX512 index register is considered a vector of sixteen signed 32-bit indexes (bit 0 not set) or eight signed 64-bit indexes (bit 0 set) The instructions all support operation masking by opmask registers. The only supported vector width is 512 bits.

Operation Basic opcode 32-bit indexes (opcode C6) 64-bit indexes (opcode C7) FP32 prefetch (W=0) FP64 prefetch (W=1) FP32 prefetch (W=0) FP64 prefetch (W=1) Prefetch into L1 cache (T0 hint) Prefetch into L2 cache (T1 hint) Prefetch into L1 cache (T0 hint) with intent to write Prefetch into L2 cache (T1 hint) with intent to write

The AVX512_4VNNIW instructions read a 128-bit data item from memory, containing 4 two-component vectors (each component being signed 16-bit). Then, for each of 4 consecutive AVX-512 registers, they will, for each 32-bit lane, interpret the lane as a two-component vector (signed 16-bit) and perform a dot-product with the corresponding two-component vector that was read from memory (the first two-component vector from memory is used for the first AVX-512 source register, and so on). These results are then accumulated into a destination vector register.

Instruction Opcode Description Dot-product of signed words with dword accumulation, 4 iterations Dot-product of signed words with dword accumulation and saturation, 4 iterations

Xeon Phi processors (from Knights Landing onwards) also featured the PREFETCHWT1 m8 instruction (opcode 0F 0D /2, prefetch into L2 cache with intent to write) − these were the only Intel CPUs to officially support this instruction, but it continues to be supported on some non-Intel processors (e.g. Zhaoxin YongFeng).

AMD instructions

Am386 SMM instructions

A handful of instructions to support System Management Mode were introduced in the Am386SXLV and Am386DXLV processors., publication #21020, rev A, apr 1997 − has SMM instruction descriptions on pages 5 and 6. They were also present in the later Am486SXLV/DXLV and Elan SC300/310 processors.AMD, Élan™SC310 Microcontroller Programmer’s Reference Manual, order no. 20665A, April 1996, section 1.9.4, page 49. Archived on 5 Sep 2024.

The SMM functionality of these processors was implemented using Intel ICE microcode without a valid license, resulting in a lawsuit that AMD lost in late 1994.Intel vs AMD, As a result of this loss, the ICE microcode was removed from all later AMD CPUs, and the SMM instructions removed with it.