The Low Pin Count (LPC) bus is a computer bus used on IBM-compatible personal computers to connect low-bandwidth devices to the CPU, such as the BIOS ROM (BIOS ROM was moved to the Serial Peripheral Interface (SPI) bus in 2006), "legacy" I/O devices (integrated into Super I/O, embedded controller, CPLD, and/or IPMI chip), and Trusted Platform Module (TPM). "Legacy" I/O devices usually include serial and parallel ports, PS/2 keyboard, PS/2 mouse, and floppy disk controller.
Most PC motherboards with an LPC bus have either a Platform Controller Hub (PCH) or a southbridge chip, which acts as the host and controls the LPC bus. All other devices connected to the physical wires of the LPC bus are peripherals.
Overview
The LPC bus was introduced by Intel in 1998 as a software-compatible substitute for the Industry Standard Architecture (ISA) bus. It resembles ISA to software, although physically it is quite different. The ISA bus has a 16-bit data bus and a 24-bit address bus that can be used for both 16-bit I/O port addresses and 24-bit memory addresses; both run at speeds up to 8.33 MHz. The LPC bus uses a heavily multiplexed four-bit-wide bus operating at four times the clock speed (33.3 MHz) to transfer addresses and data with similar performance.
LPC's main advantage is that the basic bus requires only seven signals, greatly reducing the number of pins required on peripheral chips. An integrated circuit using LPC will need 30 to 72 fewer pins than its ISA equivalent. This also makes the bus easier to route on crowded modern motherboards. The clock rate was chosen to match that of PCI in order to further ease integration. Also, LPC is intended to be a motherboard-only bus; there is no standardized connector in common use, though Intel defines one for use for debug modules. A small number of LPC peripheral daughterboards are available, with pinouts proprietary to the motherboard vendor: Trusted Platform Modules (TPMs), POST cards for displaying BIOS diagnostic codes, and ISA-compatible serial port peripherals for industrial use. Device discovery is not supported; since only motherboard devices or specific models of TPM are connected, the host firmware (BIOS, UEFI) image will include a static description of any devices and their I/O addresses expected to be present on a particular motherboard.
Signals LPC control signals are active-low, as indicated by the "#" symbol in their names. Signals are divided into three categories: Unidirectional. These are driven from a single source at all times. Open-collector. These are low-speed signals which are pulled up (to the inactive state) by the host when not in use, and may be pulled down by any device. Bidirectional. These high-speed signals are actively driven high for one cycle whenever a device is done using them, after which weak pull-up resistors hold them high until another device begins using them.
The LPC specification defines seven mandatory signals required for bidirectional data transfer: LCLK (unidirectional, from host): 33.3 MHz clock. May be connected to the conventional PCI clock (PCICLK), thereby not requiring a dedicated pin on the host (south bridge). Like PCI, other signals are driven after the falling edge of LCLK, and received after the rising edge. LRESET# (open-collector): Active-low bus reset. May be connected to PCIRST#. LFRAME# (unidirectional, from host): This active-low signal indicates the beginning of an LPC bus transaction. Only the host may initiate bus transactions. LAD[3:0] (bidirectional): These four bidirectional signals carry multiplexed address, data, and other information.
There are six additional signals defined, which are optional for LPC devices that do not require their functionality, but support for the first two is mandatory for the host: LDRQ# (unidirectional, from device): DMA/bus master request. This is an output from a device that wants to perform direct memory access, either via the Intel 8237 compatible DMA controller, or the LPC-specific bus master protocol. The host must provide one corresponding input pin per device that needs it (minimum two). SERIRQ (bidirectional): Serialized Intel 8259 compatible interrupt signal.Serialized IRQ Support For PCI Systems (Revision 6.0; September 1, 1995) One line is shared by all LPC devices and the host. Like the LAD lines, this has a weak pull-up which will maintain it high if no device is driving it. CLKRUN# (open-collector): Signal used to restart the clock in systems that can stop it for power management. Not required if the host does not stop the clock. May be connected to the equivalent PCI signal. LPME# (open-collector): Power management event, to wake the system from a sleep state. Equivalent to the PCI bus PME# signal. LSMI# (open-collector): System management interrupt request. This is only required if an LPC device needs to trigger an SMI# in response to a bus access (e.g. to perform software emulation of a missing hardware peripheral). Otherwise, the slower SERIRQ protocol can be used to request an SMI. LPCPD# (unidirectional, from host): Optional output from the host to warn the LPC device that power is about to be removed and it should not make any interrupt or DMA requests.
Timing and performance The LPC bus derives its electrical conventions from those of conventional PCI. In particular, it shares the restriction that two idle cycles are required to "turn around" any bus signal so that a different device is "speaking". In the first, the bus is actively driven high. In the second, the bus is undriven and held high by the pull-up resistors. A new device may begin sending data over the bus on the third cycle. LPC operations spend a large fraction of their time performing such turn-arounds.
As mentioned, the LPC bus is designed to have performance similar to the ISA bus. The exact data transfer rates depend on the type of bus access (I/O, memory, DMA, firmware) performed and by the speed of the host and the LPC device. All bus cycles spend a majority of their time in overhead rather than data transfer—except the 16- and 128-byte firmware read cycles, which have 17 cycles of overhead but 32 and 256 cycles (respectively) of data transfer, achieving throughputs of and . The next fastest bus cycle defined in the standard, the 32-bit ISA-style DMA write cycle, spends only 8 of 20 total clock cycles transferring data (the other 12 cycles are overhead), achieving up to 6.67 MB/s.
One of the slowest bus cycles is a simple memory read or write, where only 2 of the 17 clock cycles (plus any wait states imposed by the device) transfer data, for a transfer rate of 1.96 MB/s.
Transaction structure LPC transactions begin on a low-to-high transition of LFRAME#. While LFRAME# is low, the host places a 4-bit START code on the LAD lines. The code sent on the last cycle before LFRAME# transitions high defines the following bus transaction.
Normally, the host only holds LFRAME# low for a single clock cycle, for efficiency. An exception is the abort transaction, which may begin even in the middle of another operation. The host pulls LFRAME# low for a minimum of four clock cycles, during which any devices must cease to drive the LAD bus. On the fourth cycle, the host drives LAD high (to 1111). Upon the high-to-low transition of LFRAME#, the bus is reset to an idle state.
In almost all other cases, LPC transactions use the following general structure: START code Transaction type and address from host Data from host (if a write) Bus turnaround (2 cycles) SYNC from device (1 or more cycles) Data from device (if a read) Bus turnaround (2 cycles)
DMA transfers differ somewhat. may have multiple SYNC and data phases. § Bus master DMA has a bus turnaround immediately following the START code and no final turnaround,
The SYNC phase allows the device to insert wait states in the transaction. There are six possible SYNC values, all with even parity (even Hamming weight). Three of them end the SYNC phase, while the other three cause the host to wait for another SYNC nibble: 0000: Ready. The device is ready to proceed with the transaction. For DMA cycles, this also clears the DMA request (DREQ) signal. 0011: (not used) 0101: Short wait. Another SYNC cycle follows. At most 8 short wait cycles are permitted. 0110: Long wait. Like short wait, but the wait may be long (e.g. Enhanced Parallel Port operations) 1001: Ready more. A DMA-only code that signals "Ready" and the device requests additional DMA cycles (DREQ remains asserted). 1010: Error. The device is ready to proceed, but there was some serious error (such as a parity error) with the transfer. This is equivalent to the ISA bus IOCHK# or PCI bus SERR# signals. In the case of a read, data follows but is likely to be corrupted. 1100: (not used) 1111: Device not present. If no device responds to the transaction, the host will see this code and can abort the transaction. To accommodate slow devices, up to 2 cycles of this code are permitted before the transaction is aborted.
Applications Intel designed the LPC bus so that the system BIOS image could be stored in a single flash memory chip directly connected to the LPC bus. Intel also made it possible to put operating system images and software applications on a single flash memory chip directly connected to the LPC bus, as an alternative to a Parallel ATA port.
A CPLD or FPGA can implement an LPC host or peripheral.
The original Xbox game console has an LPC debug port that can be used to force the Xbox to boot new code.O. Theis. "Modding the XBox". section "Details of the LPC".
ISA-compatible operation All ISA-compatible LPC bus transactions use START code of 0000. During the first cycle with LFRAME# high again, the host drives a "cycle type/direction" (CTDIR) field: two bits indicating the type (I/O, memory, or DMA) and one bit indicating the direction (read from device, or write to device) of the transfer to follow. This is followed by the transfer address field, whose size depends on the type of cycle: For I/O access, the address is 16 bits, transferred most-significant nibble first over 4 cycles. For system memory access, the address is 32 bits, transferred most-significant nibble first over 8 cycles. For ISA-compatible DMA accesses, there is no address per se, but a two clock cycles transfer a nibble containing the DMA channel number, and a second nibble giving the transfer size. The memory address is programmed into the ISA-style DMA controller in the chipset or the CPU outside of the LPC bus. See below.
ISA-compatible reads and writes Memory and I/O accesses are allowed as single-byte accesses only, and operate as described in :: address, data from host if write, turnaround, SYNC, data from device if read.
If the host attempts a transfer to an unused address, no device will drive the SYNC cycles and the host will see 1111 on the LAD bus. After seeing three cycles of 1111 (two cycles are allowed, in addition to the two turn-around cycles, for a slow device to decode the address and begin driving SYNC patterns), the host will abort the operation.
ISA-compatible DMA The Platform Controller Hub (PCH) chip or the southbridge chip acts as the host and controls the LPC bus. It also acts as the central DMA controller for devices on that bus if the memory controller is in the chipset. In CPUs that contain their own memory controller(s), the DMA controller is located in the CPU. For compatibility with software originally written for systems with the ISA bus, the DMA controller contains the circuit equivalents of "legacy" onboard peripherals of the IBM PC/AT architecture, such as the two programmable interrupt controllers, the programmable interval timer, and two ISA DMA controllers, which are all involved in "ISA-style DMA".