Hardware watermarking is a technique used to protect the intellectual property (IP) of integrated circuit (IC) designs. It involves embedding hidden marks into the design’s functional or non-functional elements without impacting the intended functionality, enabling designers to prove ownership. These watermarks can be implemented at various abstraction levels—from high-level design constraints to physical layout—making them versatile for different design and verification flows. In the semiconductor supply chain, the IP owner typically sells IP cores in various forms—soft (RTL), firm (gate-level), or hard (GDSII)—to the SoC integrator, who is responsible for designing the final product. The SoC integrator acquires IPs from various vendors, integrates them with in-house designs, and performs logic synthesis to build the system’s gate-level design. Physical synthesis, including tasks like placement and routing, may be handled by the SoC integrator or outsourced to third-party service providers.M. Tanjidur Rahman, M. Sazadur Rahman, Huanyu Wang, Shahin Tajik, Waleed Khalil, Farimah Farahmandi, Domenic Forte, Navid Asadizanjani, Mark Tehranipoor, "Defense-in-depth: A recipe for logic locking to prevail", IEEE Transactions on Information Forensics and Security, Volume: 15, 2020, pp. 2681-2696 Once physical synthesis is complete, the design is sent to a semiconductor foundry for manufacturing, packaging, and testing. Since the SoC design and production cycle involves multiple untrusted parties, there is a risk that the foundry or system integrator may misuse the design, violating the original licensing agreement with the third party IP (3PIP) owner.B. Shakya, M. M. Tehranipoor, S. Bhunia, D. Forte, "Introduction to hardware obfuscation: Motivation, methods and evaluation", Hardware Protection through Obfuscation, 2017, Springer Hardware watermarking is therefore essential to address such illegal exploitations like IP theft, overuse, or copyright violations.A. Kahng, W. Mangione-Smith, "Watermarking Techniques for Intellectual Property Protection", In Proceedings of the 35th Design Automation Conference (DAC '98), 1998, pp. 776–781 An ideal watermarking technique should be easy to embed and verify while introducing minimal overhead and maintaining strong resistance to attacks. Its resiliency is often measured by two key metrics: a low probability of coincidence (to ensure uniqueness) and a high tolerance to tampering (to withstand potential removal or modification attempts). The SoC design flow using third-party IPs, along with the watermark embedding and verification process, is illustrated below in Fig. 1:
Note: Hardware watermarking is a passive defense that cannot prevent IP piracy but can prove ownership in cases of suspected infringement or illegal usage of IP within an SoC.
Process of hardware watermarking Hardware or IP core watermarking are significantly different from watermarking of images/digital content. IP Cores are usually complex in size and nature and thus require highly sophisticated mechanisms to implant signatures within their design without altering its functional behavior. Depending on the desired abstraction level and security requirements, different embedding strategies are applied using appropriate EDA tools and design techniques. Existing hardware watermarking techniques roughly fall into five categories: (a) Constraint-based (b) Finite State Machine (FSM)-based (c) Side-channel-based (d) Test structure-based (e) DSP-based watermarking.N. Nalla Anandakumar, M. Sazadur Rahman, Mridha Md Mashahedur Rahman, Rasheed Kibria, Upoma Das, Farimah Farahmandi, Fahim Rahman, Mark M. Tehranipoor, "Rethinking Watermark: Providing Proof of IP Ownership in Modern SoCs"
Constraint-based watermarking Constraint-based watermarking techniques integrate a watermark by introducing additional design constraints that encode the IP owner’s signature without altering the intended functionality of the IP.Aijiao Cui, Chip Hong Chang, and Sofiène Tahar, "IP watermarking using incremental technology mapping at logic synthesis level", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 27, Issue: 9, 2008, pp. 1565–1570Adarsh K. Jain et al., "Zero Overhead Watermarking Technique for FPGA Designs", In Proceedings of the 13th ACM Great Lakes Symposium on VLSI (GLSVLSI ’03), Washington, D. C., USA, Association for Computing Machinery, 2003, pp. 147–152Farinaz Koushanfar, Inki Hong, and Miodrag Potkonjak, "Behavioral synthesis techniques for intellectual property protection", ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume: 10, Issue: 3, 2005, pp. 523–545Seapahn Meguerdichian and Miodrag Potkonjak, "Watermarking While Preserving the Critical Path", In Proceedings of the 37th Annual Design Automation Conference (DAC ’00), Los Angeles, California, USA, Association for Computing Machinery, New York, NY, USA, 2000, pp. 108–111 These methods can be applied at multiple abstraction levels in the design flow.
At the system and behavioral synthesis levels, designers can use high-level synthesis (HLS) tools to embed watermarks early in the design process. At the system level, designers often apply node partitioning with stego constraints during Graph partitioning tasks, which can shape the design for subsequent synthesis stages. Constraint-based watermarking can also be integrated at various phases of HLS, including scheduling, register binding, functional unit binding, and interconnect binding.Mahendra Rathor, Aditya Anshul, K Bharath, Rahul Chaurasia, Anirban Sengupta, "Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores", Computers and Electrical Engineering, Volume: 105, 2023, Article No. 108476 NP-hard optimization problems—such as task scheduling, resource assignment, transformations, Resource allocation, and template mapping—are well-suited for embedding watermarks at the behavioral synthesis level.Farinaz Koushanfar, Inki Hong, and Miodrag Potkonjak, "Behavioral synthesis techniques for intellectual property protection", ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume: 10, Issue: 3, 2005, pp. 523–545 Recently, biometric-based watermarking schemes have also emerged as a unique variant of constraint-based approaches, where biometric data such as voice, fingerprints, or facial features are transformed into design constraints.Anirban Sengupta, Navonil Bhui, Vamsi Chourasia, "Hardware IP protection by exploiting IP vendor's proteogenomic BioMarker as digital watermark during behavioral synthesis", Scientific Reports, Volume: 15, 2025, Article No. 10260Anirban Sengupta, Rahul Chaurasia, and Tarun Reddy, "Contact-less palmprint biometric for securing DSP coprocessors used in CE systems", IEEE Transactions on Consumer Electronics, Volume: 67, Issue: 3, 2021, pp. 202–213Anirban Sengupta and Mahendra Rathor, "Facial biometric for securing hardware accelerators", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 29, Issue: 1, 2020, pp. 112–123Anirban Sengupta and Mahendra Rathor, "Securing hardware accelerators for CE systems using biometric fingerprinting", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 28, Issue: 9, 2020, pp. 1979–1992 For example, a voice biometric-based technique extracts features such as jitter, shimmer, pitch, and intensity from a unique voice sample to generate hardware security constraints, which are then integrated during the register allocation phase using high-level synthesis (HLS) to secure IP cores.Mahendra Rathor, Aditya Anshul, Anirban Sengupta, "Securing Reusable IP Cores using Voice Biometric based Watermark", IEEE Transactions on Dependable and Secure Computing, Volume: 21, Issue: 4, August 2024, pp. 2735–2749
At the logic synthesis level, designers can embed watermarks during the transformation of abstract RTL descriptions into optimized gate-level implementations. Multilevel logic minimization and technology mapping are key optimization tasks in this phase and are well-suited for constraint-based watermarking. For example, technology mapping can utilize disjoint closed cones within the logic network, selectively remapped based on slack and sustainability metrics to incorporate a watermark signature.A. Cui, C.-H. Chang, S. Tahar, and A. T. Abdel-Hamid, "A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 30, Issue: 5, 2011, pp. 678–690
At the physical synthesis level, Authorship signatures can be embedded during key steps—such as placement, clock tree synthesis, scan chain reordering, and routing—and later verified after fabrication.A. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang, and G. Wolfe, "Constraint-based watermarking techniques for design IP protection", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 20, Issue: 10, 2001, pp. 1236–1252Ruisi Zhang, Rachel Selina Rajarathnam, David Z Pan, Farinaz Koushanfar, "ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: XX, Issue: YY, 2025, pp. ZZZZ-AAAA, DOI: 10.XXXX/TCAD.2025.YYYYYYY Tools like Cadence Innovus and Synopsys IC Compiler support the implementation of these physical-level constraints. These techniques are not applicable to soft IPs and watermark authentication often involves partial or full reverse engineering—such as delayering and imaging of the IC layout.
Finite State Machine (FSM)-based watermarking FSM-based watermarking integrates watermark signatures into the finite state machine (FSM) of a design by modifying its state transition graph (STG) at the behavioral synthesis level. This approach leverages the state space expansion in FSMs to embed concealed watermarks and can be broadly categorized into two main techniques: transition-basedAijiao Cui, Chip-Hong Chang, Sofiene Tahar, and Amr T Abdel-Hamid, "A robust FSM watermarking scheme for IP protection of sequential circuit design", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 30, Issue: 5, 2011, pp. 678–690 and state-based.Matthew Lewandowski, Richard Meana, Matthew Morrison, and Srinivas Katkoori, "A novel method for watermarking sequential circuits", In 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, IEEE, 2012, pp. 21–24 In transition-based watermarking, designers exploit the free inputs of states in the STG to add extra transitions that carry the watermark signature. For example, flexible sets of hybrid Cellular Automaton (CA) rules can manage don’t-care states to conceal the watermark, which can then be authenticated using variable challenge-response pairs (CRPs). State-based watermarking expands the state space of the FSM to hide the watermark signature among new states without affecting design functionality. These methods allow IP owners to embed authorship claims directly into the control logic of their designs, offering strong resistance to removal and tampering attacks.
Side-channel-based watermarking