Synchronous dynamic random-access memory (synchronous dynamic RAM or SDRAM) is any DRAM where the operation of its external pin interface is coordinated by an externally supplied clock signal.
DRAM integrated circuits (ICs) produced from the early 1970s to the early 1990s used an asynchronous interface, in which input control signals have a direct effect on internal functions delayed only by the trip across its semiconductor pathways. SDRAM has a synchronous interface, whereby changes on control inputs are recognised after a rising edge of its clock input. In SDRAM families standardized by JEDEC, the clock signal controls the stepping of an internal finite-state machine that responds to incoming commands. These commands can be pipelined to improve performance, with previously started operations completing while new commands are received. The memory is divided into several equally sized but independent sections called banks, allowing the device to operate on a memory access command in each bank simultaneously and speed up access in an interleaved fashion. This allows SDRAMs to achieve greater concurrency and higher data transfer rates than asynchronous DRAMs could.
Pipelining means that the chip can accept a new command before it has finished processing the previous one. For a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written into the memory array. For a pipelined read, the requested data appears a fixed number of clock cycles (latency) after the read command, during which additional commands can be sent.
History
The earliest DRAMs were often synchronized with the CPU clock (clocked) and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation. In the late 1980s IBM had built DRAMs using a dual-edge clocking feature and presented their results at the International Solid-State Circuits Convention in 1990. However, it was standard DRAM, not SDRAM.
The first commercial SDRAM was the Samsung KM48SL2000 memory chip, which had a capacity of 16Mbit. It was manufactured by Samsung Electronics using a CMOS (complementary metal–oxide–semiconductor) fabrication process in 1992, and mass-produced in 1993. By 2000, SDRAM had replaced virtually all other types of DRAM in modern computers, because of its greater performance.
SDRAM latency is not inherently lower (faster access times) than asynchronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous burst EDO DRAM due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective bandwidth.
Double data rate SDRAM, known as DDR SDRAM, was first demonstrated by Samsung in 1997. Samsung released the first commercial DDR SDRAM chip (64Mbit) in June 1998, followed soon after by Hyundai Electronics (now SK Hynix) the same year.
Today, virtually all SDRAM is manufactured in compliance with standards established by JEDEC, an electronics industry association that adopts open standards to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for DDR, DDR2 and DDR3 SDRAM.
SDRAM is also available in registered varieties, for systems that require greater scalability such as servers and workstations.
Today, the world's largest manufacturers of SDRAM include SK Hynix, Samsung Electronics, Micron Technology, ChangXin Memory Technologies, and Nanya Technology.
Timing There are several limits on DRAM performance. Most noted is the read cycle time, the time between successive read operations to an open row. This time decreased from 15 ns for 66 MHz SDRAM (1 MHz = 106 Hz) to 5 ns for DDR-400, but remained relatively unchanged through DDR2-800 and DDR3-1600 generations. However, by operating the interface circuitry at increasingly higher multiples of the fundamental read rate, the achievable bandwidth has increased rapidly.
Another limit is the CAS latency, the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through the last few generations of DDR SDRAM.
In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.
SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100 MHz SDRAM chips first appeared, some manufacturers sold "100 MHz" modules that could not reliably operate at that clock rate. In response, Intel published the PC100 standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100 MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100 MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (PC66, PC100 or PC133 – although the actual meaning of the numbers has changed).
Control signals All commands are timed relative to the rising edge of a clock signal. In addition to the clock, there are six control signals, mostly active low, which are sampled on the rising edge of the clock: CKE clock enable. When this signal is low, the chip behaves as if the clock has stopped. No commands are interpreted and command latency times do not elapse. The state of other control lines is not relevant. The effect of this signal is actually delayed by one clock cycle. That is, the current clock cycle proceeds as usual, but the following clock cycle is ignored, except for testing the CKE input again. Normal operations resume on the rising edge of the clock after the one where CKE is sampled high. Put another way, all other chip operations are timed relative to the rising edge of a masked clock. The masked clock is the logical AND of the input clock and the state of the CKE signal during the previous rising edge of the input clock. chip select. When this signal is high, the chip ignores all other inputs (except for CKE), and acts as if a NOP command is received. DQM data mask. (The letter Q appears because, following digital logic conventions, the data lines are known as "DQ" lines.) When high, these signals suppress data I/O. When accompanying write data, the data is not actually written to the DRAM. When asserted high two cycles before a read cycle, the read data is not output from the chip. There is one DQM line per 8 bits on a x16 memory chip or DIMM.
Command signals , row address strobe. Despite the name, this is not a strobe, but rather simply a command bit. Along with and , this selects one of eight commands. , column address strobe. This is also not a strobe, rather a command bit. Along with and , this selects one of eight commands. , write enable. Along with and , this selects one of eight commands. It generally distinguishes read-like commands from write-like commands.
Bank selection (BAn) SDRAM devices are internally divided into either two, four or eight independent internal data banks. One to three bank address inputs (BA0, BA1 and BA2) are used to select which bank a command is directed toward.
Addressing (A10/An) Many commands also use an address presented on the address input pins. Some commands, which either do not use an address, or present a column address, also use A10 to select variants.
Commands The SDR SDRAM commands are defined as follows:
BAn A10 An Command H x x x x x x Command inhibit (no operation) L H H H x x x No operation L H H L x x x Burst terminate: stop a burst read or burst write in progress L H L H bank L column Read: read a burst of data from the currently active row L H L H bank H column Read with auto precharge: as above, and precharge (close row) when done L H L L bank L column Write: write a burst of data to the currently active row L H L L bank H column Write with auto precharge: as above, and precharge (close row) when done L L H H bank row Active (activate): open a row for read and write commands L L H L bank L x Precharge: deactivate (close) the current row of selected bank L L H L x H x Precharge all: deactivate (close) the current row of all banks L L L H x x x Auto refresh: refresh one row of each bank, using an internal counter. All banks must be precharged. L L L L 0 0 mode Load mode register: A0 through A9 are loaded to configure the DRAM chip.The most significant settings are CAS latency (2 or 3 cycles) and burst length (1, 2, 4 or 8 cycles)
All SDRAM generations (SDR and DDRx) use essentially the same commands, with the changes being: Additional address bits to support larger devices Additional bank select bits Wider mode registers (DDR2 and up use 13 bits, A0–A12) Additional extended mode registers (selected by the bank address bits) DDR2 deletes the burst terminate command; DDR3 reassigns it as "ZQ calibration" DDR3 and DDR4 use A12 during read and write command to indicate "burst chop", half-length data transfer DDR4 changes the encoding of the activate command. A new signal controls it, during which the other control lines are used as row address bits 16, 15 and 14. When is high, other commands are the same as above.
Construction and operation
As an example, a 512 MB SDRAM DIMM (which contains 512 MB), might be made of eight or nine SDRAM chips, each containing 512 Mbit of storage, and each one contributing 8 bits to the DIMM's 64- or 72-bit width. A typical 512 Mbit SDRAM chip internally contains four independent 16 MB memory banks. Each bank is an array of 8,192 rows of 16,384 bits each. (2048 8-bit columns). A bank is either idle, active, or changing from one to the other.
The active command activates an idle bank. It presents a two-bit bank address (BA0–BA1) and a 13-bit row address (A0–A12), and causes a read of that row into the bank's array of all 16,384 column sense amplifiers. This is also known as "opening" the row. This operation has the side effect of refreshing the dynamic (capacitive) memory storage cells of that row.
Once the row has been activated or "opened", read and write commands are possible to that row. Activation requires a minimum amount of time, called the row-to-column delay, or tRCD before reads or writes to it may occur. This time, rounded up to the next multiple of the clock period, specifies the minimum number of wait cycles between an active command, and a read or write command. During these wait cycles, additional commands may be sent to other banks; because each bank operates completely independently.
Both read and write commands require a column address. Because each chip accesses eight bits of data at a time, there are 2,048 possible column addresses thus requiring only 11 address lines (A0–A9, A11).
When a read command is issued, the SDRAM will produce the corresponding output data on the DQ lines in time for the rising edge of the clock a few clock cycles later, depending on the configured CAS latency. Subsequent words of the burst will be produced in time for subsequent rising clock edges.