Unums (universal numbers) are a family of number formats and arithmetic for implementing real numbers on a computer, proposed by John L. Gustafson in 2015. They are designed as an alternative to the ubiquitous IEEE 754 floating-point standard. The latest version is known as posits.
Type I Unum The first version of unums, formally known as Type I unum, was introduced in Gustafson's book The End of Error as a superset of the IEEE-754 floating-point format. The defining features of the Type I unum format are: a variable-width storage format for both the significand and exponent, and a u-bit, which determines whether the unum corresponds to an exact number (u = 0), or an interval between consecutive exact unums (u = 1). In this way, the unums cover the entire extended real number line [−∞,+∞].
For computation with the format, Gustafson proposed using interval arithmetic with a pair of unums, what he called a ubound, providing the guarantee that the resulting interval contains the exact solution.
William M. Kahan and Gustafson debated unums at the Arith23 conference.
Type II Unum Type II Unums were introduced in 2016 as a redesign of Unums that broke IEEE-754 compatibility. In addition to the sign bit and the interval bit mentioned earlier, the Type II Unum uses a bit to indicate inversion. These three operations make it possible, starting from a finite set of points between one and infinity, to quantify the entire projective line except for four points: the two exceptions, 0 and ∞, and then 1 and −1. This set of points is chosen arbitrarily, and arithmetic operations involving them are not performed logically but rather by using a lookup table. The size of such a table becomes prohibitive for an encoding format spanning multiple bytes. This challenge necessitated the development of the Type III Unum, known as the posit, discussed below.
Posit (Type III Unum) In February 2017, Gustafson officially introduced Type III unums (posits), for fixed floating-point-like values and valids for interval arithmetic. In March 2022, a standard was ratified and published by the Posit Working Group.
Posits are a hardware-friendly version of unum where difficulties faced in the original type I unum due to its variable size are resolved. Compared to IEEE 754 floats of similar size, posits offer a bigger dynamic range and more fraction bits for values with magnitude near 1 (but fewer fraction bits for very large or very small values), and Gustafson claims that they offer better accuracy. Studies confirm that for some applications, posits with quire out-perform floats in accuracy. Posits have superior accuracy in the range near one, where most computations occur. This makes it very attractive to the current trend in deep learning to minimize the number of bits used. It potentially helps any application to accelerate by enabling the use of fewer bits (since it has more fraction bits for accuracy) reducing network and memory bandwidth and power requirements.
The format of an n-bit posit is given a label of "posit" followed by the decimal digits of n (e.g., the 16-bit posit format is "posit16") and consists of four sequential fields:
sign: 1 bit, representing an unsigned integer s regime: at least 2 bits and up to (n − 1), representing an unsigned integer r as described below exponent: generally 2 bits as available after regime, representing an unsigned integer e fraction: all remaining bits available after exponent, representing a non-negative real dyadic rational f less than 1
The regime field uses unary coding of k identical bits, followed by a bit of opposite value if any remaining bits are available, to represent an unsigned integer r that is −k if the first bit is 0 or k − 1 if the first bit is 1. The sign, exponent, and fraction fields are analogous to IEEE 754 sign, exponent, and significand fields (respectively), except that the posit exponent and fraction fields may be absent or truncated and implicitly extended with zeroes—an absent exponent is treated as 002 (representing 0), a one-bit exponent E1 is treated as E102 (representing the integer 0 if E1 is 0 or 2 if E1 is 1), and an absent fraction is treated as 0. Negative numbers (s is 1) are encoded as 2's complements.
The two encodings in which all non-sign bits are 0 have special interpretations:
If the sign bit is 1, the posit value is NaR ("not a real") If the sign bit is 0, the posit value is 0 (which is unsigned and the only value for which the sign function returns 0)
Otherwise, the posit value is equal to , in which r scales by powers of 16, e scales by powers of 2, f distributes values uniformly between adjacent combinations of (r, e), and s adjusts the sign symmetrically about 0.
Examples + Type(positn) Binary Value Notes 1 0…NaRanything not mathematically definable as a unique real number 0 0… 0 10… 1 10… 0 01 11 0… 0 0…1smallest positive value 0 1…largest positive valueposit80 0000001smallest positive valueposit80 1111111largest positive valueposit160 000000000000001smallest positive valueposit160 111111111111111largest positive valueposit32smallest positive valueposit32largest positive value
Quire For each positn type of precision , the standard defines a corresponding "quire" type quire n of precision , used to accumulate exact sums of products of those posits without rounding or overflow in dot products for vectors of up to 231 or more elements (the exact limit is ). The quire format is a two's complement signed integer, interpreted as a multiple of units of magnitude except for the special value with a leading sign bit of 1 and all other bits equal to 0 (which represents NaR). Quires are based on the work of Ulrich W. Kulisch and Willard L. Miranker.
Valid Valids are described as a Type III Unum mode that bounds results in a given range.
Implementations Several software and hardware solutions implement posits. The first complete parameterized posit arithmetic hardware generator was proposed in 2018.
Unum implementations have been explored in Julia and MATLAB. A C++ version with support for any posit sizes combined with any number of exponent bits is available. A fast implementation in C, SoftPosit, provided by the NGA research team based on Berkeley SoftFloat adds to the available software implementations.
Project authorTypePrecisionsQuire Support?SpeedTestingNotesGP-GPU VividSparksWorld's first FPGA GPGPU32 ~3.2 TPOPS Exhaustive. No known bugs. RacEr GP-GPU has 512 coresSoftPosit A*STARC library based on Berkeley SoftFloat C++ wrapper to override operators Python wrapper using SWIG of SoftPosit8, 16, 32 published and complete; ~60 to 110 MPOPS on x86 core (Broadwell)8: Exhaustive; 16: Exhaustive except FMA, quire 32: Exhaustive test is still in progress. No known bugs. license. Fastest and most comprehensive C library for posits presently. Designed for plug-in comparison of IEEE floats and posits.posit4.nb A*STARMathematica notebookAll < 80 KPOPSExhaustive for low precisions. No known bugs. (MIT license). Original definition and prototype. Most complete environment for comparing IEEE floats and posits. Many examples of use, including linear solversposit-javascript A*STARJavaScript widgetConvert decimal to posit 6, 8, 16, 32; generate tables 2–17 with es 1–4. Fully testedTable generator and conversionUniversal Stillwater Supercomputing, IncC++ template library C library Python wrapper Golang libraryArbitrary precision posit float valid (p) Unum type 1 (p) Unum type 2 (p)Arbitrary quire configurations with programmable capacityposit<4,0> 1 GPOPS posit<8,0> 130 MPOPS posit<16,1> 115 MPOPS posit<32,2> 105 MPOPS posit<64,3> 50 MPOPS posit<128,4> 1 MPOPS posit<256,5> 800 KPOPSComplete validation suite for arbitrary posits Randoms for large posit configs. Uses induction to prove nbits+1 is correct no known bugs. MIT license. Fully integrated with C/C++ types and automatic conversions. Supports full C++ math library (native and conversion to/from IEEE). Runtime integrations: MTL4/MTL5, Eigen, Trilinos, HPR-BLAS. Application integrations: G+SMO, FDBB, FEniCS, ODEintV2, TVM.ai. Hardware accelerator integration (Xilinx, Intel, Achronix).Speedgo Chung Shin YeePython libraryAll ~20 MPOPSExtensive; no known bugs (MIT license)softposit-rkt David ThienSoftPosit bindings for RacketAll sfpy Bill ZornSoftPosit bindings for PythonAll ~20–45 MPOPS on 4.9 GHz Skylake core positsoctave Diego CoelhoOctave implementationAll Limited Testing; no known bugsSigmoid Numbers Isaac YonemotoJulia libraryAll <32, all ES No known bugs (posits). Division bugs (valids)Leverages Julia's templated mathematics standard library, can natively do matrix and tensor operations, complex numbers, FFT, DiffEQ. Support for validsFastSigmoid Isaac YonemotoJulia and C/C++ library8, 16, 32, all ES Known bug in 32-bit multiplicationUsed by LLNL in shock studiesSoftPosit.jl Milan KlöwerJulia libraryBased on softposit; 8-bit (es=0..2) 16-bit (es=0..2) 24-bit (es=1..2) 32-bit (es=2) Similar to A*STAR "SoftPosit" (Cerlane Leong)Yes: Posit (8,0), Posit (16,1), Posit (32,2) Other formats lack full functionality. Issues and suggestions on GitHub. This project was developed due to the fact that SigmoidNumbers and FastSigmoid by Isaac Yonemoto is not maintained currently.
Supports basic linear algebra functions in Julia (Matrix multiplication, Matrix solve, Elgen decomposition, etc.)PySigmoid Ken MercadoPython libraryAll < 20 MPOPS (MIT license). Easy-to-use interface. Neural net example. Comprehensive functions support.cppPosit Federico Rossi, Emanuele RuffaldiC++ library4 to 64 (any es value); "Template version is 2 to 63 bits" A few basic tests4 levels of operations working with posits. Special support for NaN types (non-standard)bfp:Beyond Floating Point Clément GuérinC++ library Bugs found; status of fixes unknownSupports + – × ÷ √ reciprocal, negate, compareVerilog.jl Isaac YonemotoJulia and Verilog8, 16, 32, ES=0 Comprehensively tested for 8-bit, no known bugsIntended for Deep Learning applications Addition, Subtraction and Multiplication only. A proof of concept matrix multiplier has been built, but is off-spec in its precisionLombiq Arithmetics Lombiq TechnologiesC# with Hastlayer for hardware generation8, 16, 32. (64bits in progress) 10 MPOPS Click here for more Requires Microsoft .Net APIsDeepfloatJeff Johnson, FacebookSystemVerilog (parameterized SystemVerilog) (RTL for FPGA/ASIC designs)LimitedDoes not strictly conform to posit spec. Supports +,-,/,*. Implements both logarithmic posit and normal, "linear" posits License: CC-BY-NC 4.0 at presentTokyo TechFPGA16, 32, extendable "2 GHz", not translated to MPOPS ; known rounding bugsYet to be open-sourcePACoGen: Posit Arthmetic Core GeneratorManish Kumar JaiswalVerilog HDL for Posit Arithmetic precision. Able to generate any combination of word-size (N) and exponent-size (ES) Speed of design is based on the underlying hardware platform (ASIC/FPGA)Exhaustive tests for 8-bit posit. Multi-million random tests are performed for up to 32-bit posit with various ES combinationsIt supports rounding-to-nearest rounding method.Vinay Saxena, Research and Technology Centre, Robert Bosch, India (RTC-IN) and Farhad Merchant, RWTH Aachen UniversityVerilog generator for VLSI, FPGAAll Similar to floats of same bit sizeN=8 - ES=2 | N=7,8,9,10,11,12 Selective (20000*65536) combinations for - ES=1 | N=16To be used in commercial products. To the best of our knowledge. ***First ever integration of posits in RISC-V***Posit-enabled RISC-V core (Sugandha Tiwari, Neel Gala, Chester Rebeiro, V.Kamakoti, IIT MADRAS)BSV (Bluespec System Verilog) Implementation32-bit posit with (es=2) and (es=3) Verified against SoftPosit for (es=2) and tested with several applications for (es=2) and (es=3). No known bugs.First complete posit-capable RISC-V core. Supports dynamic switching between (es=2) and (es=3). More info here.PERCIVAL