National Semiconductor's SC/MP (pronounced scamp) for Simple Cost-effective Micro Processor, is an early 8-bit microprocessor which became available in April 1976. It was designed to allow systems to be implemented with the minimum number of additional support chips. SC/MP included bus-access control signals that allowed several processors to share a common memory bus in a daisy-chained multiprocessor arrangement, or to support direct memory access hardware.
The SC/MP was followed by the SC/MP-II, also known as the INS8060. National Semiconductor later introduced the 70-Series (also known as the INS8070 Series). Some later sources refer to this family as “SC/MP III” or “SC/MP-3”, terminology not used in contemporary National Semiconductor documentation.
The programmer-visible model comprises an 8-bit accumulator, an 8-bit extension register, an 8-bit status register, and four 16-bit pointer registers, one of which is used as the program counter. Memory-reference addressing is page-based, with address arithmetic performed on the low 12 bits of the address.
Designed to be as low-cost as possible, the SC/MP emphasized simple control logic and built-in multiprocessor bus arbitration. It is significantly slower than contemporary designs like the Intel 8080 or MOS 6502. Another oddity was that the program counter could only increment the lower 12-bits of the 16-bit address; the upper 4-bits had to be set using special instructions. The result was that instructions accessed main memory as sixteen 4 KB "pages" and reaching memory outside those pages required multiple instructions.
The combination of slow speed and paged memory limited its attractiveness outside the embedded markets it was aimed at, and in this market it competed against the Fairchild F8 which had a number of useful additional features and cost less than a dollar more at 100-unit quantities. The system saw relatively little use. Signetics was identified as an authorized second source and published SC/MP-II documentation, but it is unclear whether it manufactured any SC/MP devices.
Design The SC/MP instruction set consists of 46 instructions.
+ NS SC/MP registers Main registers 7 6 5 4 3 2 1 0 (bit position) AC Accumulator E Extension Pointer registers 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position) page fieldbits 15–12 12-bit address within pagebits 11–0 P0/PC Program Counter P1 Pointer 1 P2 Pointer 2 P3 Pointer 3 Status Registers 7 6 5 4 3 2 1 0 (bit position) CY/L OV SB SA IE F2 F1 F0 Status Register (SR)
ALU and main registers The arithmetic logic unit (ALU) is accumulator-based, with a single 8-bit accumulator, AC. National Semiconductor described the SC/MP's arithmetic as parallel, binary, fixed-point and two's-complement, with support for two-digit BCD addition using the (Decimal Add Extension) instruction.
A second 8-bit register, "Extension", or E, is an 8-bit auxiliary to the accumulator (AC), but unlike AC, it is not a general-purpose register. It cannot be loaded directly from memory and is accessed only through a small set of single-byte instructions that operate between E and AC.
Two of these, and , move or exchange data between the two registers. The others, , , , , , and use the contents of E as the second operand in arithmetic or logical operations on AC.
The E register also serves several other roles in the architecture. It functions as the shift register for the serial I/O system, used by the instruction. Each execution shifts E right by one bit, placing the least-significant bit on the pin and shifting in a new bit from . Transmitting or receiving a full byte requires repeated instructions. To transfer serial data to or from memory, values can be exchanged between E and AC. Logical operations on AC can then test or mask values read into E.
The E register can also be used in place of the displacement byte in PC-relative, indexed, and auto-indexed memory-reference instructions. In these forms, the usable literal displacement range is effectively −127 to +127. The byte value hexadecimal is reserved as a special marker, so it does not mean a literal displacement of −128. Instead, it tells the processor to use the contents of E as the displacement when forming the effective address.
The separate Status Register (SR) is 8 bits wide. Its three least-significant bits, 0 through 2, are available on control-output pins, providing an easy way to output single-bit signals. Bits 4 and 5 reflect the external Sense A and Sense B input pins. These bits can be read by copying SR to AC with , but they are read-only inputs and are not changed by . When interrupts are enabled, Sense A also serves as the interrupt request input. Bit 3 is the Interrupt Enable bit, which can be cleared with , set with , or changed by copying AC to the writable status bits with . Bits 6 and 7 are the overflow flag and carry/link flag. Although there is no explicit zero flag, zero is determined from the current content of AC.
Addressing and pointer registers
Like most 8-bit microprocessors of the era, the SC/MP is based around a 16-bit address bus and an 8-bit data bus. To reduce pin count, the external address bus contains only 12 pins, multiplexing 4 pins on the data bus to create a complete 16-bit address. The processor only directly modifies the lower 12-bits of the program counter. There are separate instructions to set the upper four bits by copying an 8-bit value into the high byte. This provides a memory map of sixteen four-kilobyte pages. PC-relative or indexed addressing cannot refer to code or data outside the current 4 KB page. This leads to a curiosity of the design: when the program counter reaches the end of a page, it does not move to the next page, it returns to the start of the current page.
Addressing is further limited by the two-byte instruction format used by most memory-reference instructions, which places the opcode in one byte and a displacement in the second. National Semiconductor described the displacement field as an 8-bit two's-complement value with an encoded range of −128 to +127 from the selected pointer-register value. In memory-reference instruction forms, however, the byte value hexadecimal is a special marker rather than an available literal displacement of −128. It causes the processor to use the contents of the E register as the displacement source when forming the effective address. For instance, an address might refer to a location in memory by saying it is +10 locations from the value in the program counter, or -10 from the value in one of the 16-bit pointer registers. To access a location outside the PC-relative or indexed displacement range, or outside the current 4 KB page, a suitable address has to be explicitly loaded into one of the pointer registers. Because the registers are 16-bit, and the accumulator that loads values is 8-bit, setting a complete address requires several instructions.
As indexed addressing is critical to the addressing model, the SC/MP included four 16-bit pointer registers, P0 through P3. P0 is the program counter. By convention, P1 is normally used as a pointer into ROM, P2 into RAM, and P3 was used to store an address during interrupts and subroutine calls. The SC/MP does not have a hardware stack or dedicated stack pointer for storing return addresses. Subroutine linkage instead uses pointer registers, especially P3 with the instruction, so nested calls or interrupt handling requires return addresses to be saved explicitly, or by a software stack convention.
There are four primary addressing modes, PC-relative, indexed, immediate (meaning a constant in the instruction's second byte as opposed to an offset), and auto-indexed. PC-relative addressing is actually the same as indexed, selecting P0 as the pointer register.
Auto-indexing aids in the construction of loops. In the auto-indexed form, prefixed with , the selected pointer register is also modified by the displacement. If the displacement is negative, the pointer register is modified before the memory access. If the displacement is zero or positive, the current pointer-register value is used as the effective address, and the pointer register is modified after the memory access. This removes the need for a separate instruction to change the value in the register, so one could store the starting value of a block of data in memory in a pointer register and then loop through all of the data. If the offset is negative, as in , it performs the decrement before accessing the final value. If it is positive, as in , it does a post-increment. This predecrement-postincrement behavior makes it possible to create a LIFO stack. Top of stack is accessed with . Stack space can be allocated and released with larger offsets such as and , respectively.
The memory increment/decrement instructions and , and the transfer instructions , , , and , are documented separately from the memory-reference instructions. National's source forms for these instructions include and . The auto-indexed form is not supported.
Interrupt handling The system includes automatic handling of interrupts on the Sense A line. If Sense A is active when the Interrupt Enable flag, IE, is set, the SC/MP completes the current instruction, clears IE to disable further interrupts, and exchanges the contents of PC and P3. Execution then resumes using the normal SC/MP increment-before-fetch behaviour, so P3 must have been prepared with the address immediately preceding the interrupt handler entry point, subject to the processor's 4 KB page-addressing rules.
Because interrupt entry is implemented as an automatic operation, P3 conventionally serves as the interrupt-link register and is unavailable for general use while interrupts are enabled.
The system does not include the equivalent of a return-from-interrupt. This can be performed with a instruction, which exchanges the contents of P3 and the program counter. This restores the interrupted program's execution address while storing the current interrupt-handler address in P3, allowing execution to continue where it left off. However, this leaves the wrong address in P3, not the start of the interrupt handler, but the end. To address this, the common solution is to place the that returns to the main code one instruction above the handler entry point, rather than at the end. When the handler completes, it jumps back to this instruction, so when is executed, the PC is pointed one location before the proper entry point. Because the SC/MP increments the program counter before instruction fetch, the next interrupt then enters the handler at the correct entry point. This "exit handler" normally also sets the IE to 1 with to re-enable interrupts.
Interrupt entry itself is simple, but saving processor state is left to software. National Semiconductor's example interrupt save sequence for the SC/MP requires 17 instructions and 26 bytes of object code, compared with four instructions and four bytes for the Intel 8080.
Bus control
A feature of the SC/MP family was its bus-access logic, using bus-request, enable-input and enable-output signals. In the original PMOS SC/MP documentation these are named BREQ, ENIN and ENOUT; in SC/MP-II / INS8060 documentation the corresponding active-low signals are named NBREQ, NENIN and NENOUT. These signals supported external direct memory access (DMA) hardware and allowed multiple SC/MP processors to be connected in a daisy-chained shared-bus arrangement. National Semiconductor's PMOS SC/MP documentation gives example DMA and multiprocessor configurations, contrasting an external DMA controller with the SC/MP's built-in bus-access logic. The INS8060 datasheet documents the corresponding SC/MP-II bus-access signals, NBREQ, NENIN and NENOUT, for DMA and multiprocessor use. Williamson and Dale give the equivalent SC/MP-II explanation in the context of the MK14.