The media-independent interface (MII) was originally defined as a standard interface to connect a Fast Ethernet (i.e., ) medium access control (MAC) block to a PHY chip. The MII is standardized by IEEE 802.3u and connects different types of PHYs to MACs. Being media independent means that different types of PHY devices for connecting to different media (i.e. twisted pair, fiber optic, etc.) can be used without redesigning or replacing the MAC hardware. Thus, any MAC may be used with any PHY, independent of the network signal transmission medium.

The MII can be used to connect a MAC to an external PHY using a pluggable connector or directly to a PHY chip on the same PCB. On older PCs, the CNR connector Type B carried MII signals.

Network data on the interface is framed using the IEEE Ethernet standard. As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol-specific data and a cyclic redundancy check (CRC). The original MII transfers network data using 4-bit nibbles in each direction (4 transmit data bits, 4 receive data bits). The data is clocked at 25 MHz to achieve throughput. The original MII design has been extended to support reduced signals and increased speeds. The abbreviation xMII stands for generic media-independent interface, which includes:

Reduced media-independent interface (RMII) Gigabit media-independent interface (GMII) Reduced gigabit media-independent interface (RGMII) Serial media-independent interface (SMII) Serial gigabit media-independent interface (serial GMII, SGMII) High serial gigabit media-independent interface (HSGMII) Quad serial gigabit media-independent interface (QSGMII) Penta serial gigabit media-independent interface (PSGMII) 10-gigabit media-independent interface (XGMII)

The Management Data Input/Output (MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. At power up, using autonegotiation, the PHY usually adapts to whatever it is connected to unless settings are altered via the MDIO interface.

Standard MII The standard MII features a small set of registers:

+ MII registers Address Name 0 Basic Mode Configuration 1 Status Word 2 PHY Identifier 3 4 Auto-Negotiation Advertisement 5 Auto-Negotiation Link Partner Base Page Ability 6 Auto-Negotiation Expansion 7 Auto-Negotiation Next Page Transmit 8 Auto-Negotiation Link Partner Received Next Page 9 MASTER-SLAVE Control Register 10 MASTER-SLAVE Status Register 11 PSE Control Register 12 PSE Status Register 13 MMD Access Control Register 14 MMD Access Address Data Register 15 Reserved 16-31 Vendor specific

The MII Status Word is the most useful datum, since it may be used to detect whether an Ethernet NIC is connected to a network. It contains a bit field with the following information:

+ MII Status Word Bit value Meaning 0x8000 Capable of 100BASE-T4 0x6000 Capable of 100BASE-TX full/half duplex 0x1800 Capable of 10BASE-T full/half duplex 0x0600 Capable of 100BASE-T2 full/half duplex 0x0100 Extended status (Gigabit Ethernet) register exists 0x0080 Capable of unidirectional operation 0x0040 Management frame preamble suppression permitted 0x0020 Autonegotiation complete 0x0010 Remote fault 0x0008 Capable of Autonegotiation 0x0004 Link established 0x0002 Jabber detected 0x0001 Extended MII registers exist

Transmitter signals Signal name Description Direction TX_CLK Transmit clock PHY to MAC TXD0 Transmit data bit 0 (transmitted first) MAC to PHY TXD1 Transmit data bit 1 MAC to PHY TXD2 Transmit data bit 2 MAC to PHY TXD3 Transmit data bit 3 MAC to PHY TX_EN Transmit enable MAC to PHY TX_ER Transmit error (optional) MAC to PHY

The transmit clock is a free-running clock generated by the PHY based on the link speed (25 MHz for , 2.5 MHz for ). The remaining transmit signals are driven by the MAC synchronously on the rising edge of TX_CLK. This arrangement allows the MAC to operate without having to be aware of the link speed. The transmit enable signal is held high during frame transmission and low when the transmitter is idle.

Transmit error may be raised for one or more clock periods during frame transmission to request the PHY to deliberately corrupt the frame in some visible way that precludes it from being received as valid. This may be used to abort a frame when some problem is detected after transmission has already started. The MAC may omit the signal if it has no use for this functionality, in which case the signal should be tied low for the PHY.

More recently, raising transmit error outside frame transmission is used to indicate the transmit data lines are being used for special-purpose signalling. Specifically, the data value 0b0001 (held continuously with TX_EN low and TX_ER high) is used to request an EEE-capable PHY to enter low power mode.

Receiver signals Signal name Description Direction RX_CLK Receive clock PHY to MAC RXD0 Receive data bit 0 (received first) PHY to MAC RXD1 Receive data bit 1 PHY to MAC RXD2 Receive data bit 2 PHY to MAC RXD3 Receive data bit 3 PHY to MAC RX_DV Receive data valid PHY to MAC RX_ER Receive error PHY to MAC CRS Carrier sense PHY to MAC COL Collision detect PHY to MAC

The first seven receiver signals are entirely analogous to the transmitter signals, except RX_ER is not optional and used to indicate the received signal could not be decoded to valid data. The receive clock is recovered from the incoming signal during frame reception. When no clock can be recovered (i.e. when the medium is silent), the PHY must present a free-running clock as a substitute.

The receive data valid signal (RX_DV) is not required to go high immediately when the frame starts, but must do so in time to ensure the "start of frame delimiter" byte is included in the received data. Some of the preamble nibbles may be lost.

Similar to transmit, raising RX_ER outside a frame is used for special signaling. For receive, two data values are defined: 0b0001 to indicate the link partner is in EEE low power mode, and 0b1110 for a false carrier indication.

The CRS and COL signals are asynchronous to the receive clock, and are only meaningful in half-duplex mode. Carrier sense is high when transmitting, receiving, or the medium is otherwise sensed as being in use. If a collision is detected, COL also goes high while the collision persists.

In addition, the MAC may weakly pull-up the COL signal, allowing the combination of COL high with CRS low (which a PHY will never produce) to serve as an indication of an absent or disconnected PHY.

Management signals

Signal name Description Direction MDIO Management data Bidirectional MDC Management data clock MAC to PHY

MDC and MDIO constitute a synchronous serial data interface similar to I²C. As with I²C, the interface is a multidrop bus so MDC and MDIO can be shared among multiple PHYs.

Limitations The interface requires 18 signals, out of which only two (MDIO and MDC) can be shared among multiple PHYs. This presents a problem, especially for multiport devices; for example, an eight-port switch using MII would need 8 × 16 + 2 = 130 signals.

Reduced media-independent interface

Reduced media-independent interface (RMII) is a standard that was developed to reduce the number of signals required to connect a PHY to a MAC. This helps reduce cost and complexity for network hardware, especially in the context of microcontrollers with built-in MAC, FPGAs, multiport switches or repeaters, and PC motherboard chipsets. The following changes from the MII standard cut the number of required signals from 18 in half to only 9: MII's two clocks (TXCLK and RXCLK) are replaced by a single clock (REF_CLK) used as a reference for both receiver and transmitter signals. The clock frequency is doubled from 25 MHz to 50 MHz, while both data paths are halved from 4 bits to 2 bits. Data is clocked out 2 bits at a time (vs 4 bits at a time in MII) or 1 bit at a time for serial network interface (SNI) mode ( only). Data is still sampled on the rising edge only (i.e., it is not double-pumped). RXDV and CRS signals are multiplexed into one signal. The COL signal is removed. RX_ER became optional. Additionally, on multiport devices (such as a switch), MDIO, MDC, and REF_CLK may be shared, leaving 6 or 7 pins per port. + Reduced media-independent interface (RMII) signals Signal name Description Direction REF_CLK Continuous 50 MHz reference clock Reference clock may be an input on both devices from an external clock source, or may be driven from the MAC to the PHY, or may be driven from the PHY to the MAC TXD0 Transmit data bit 0 (transmitted first) MAC to PHY TXD1 Transmit data bit 1 MAC to PHY TX_EN When high, clock data on TXD0 and TXD1 to the transmitter MAC to PHY RXD0 Receive data bit 0 (received first) PHY to MAC RXD1 Receive data bit 1 PHY to MAC CRS_DV Carrier Sense (CRS) and RX_Data Valid (RX_DV) multiplexed on alternate clock cycles. In mode, it alternates every 10 clock cycles. PHY to MAC RX_ER Receive error (optional) PHY to MAC MDIO Management data Bidirectional MDC Management data clock. MAC to PHY

Note: the REF_CLK operates at 50 MHz in both mode and mode. The transmitting side (PHY or MAC) must keep all signals valid for 10 clock cycles in mode. The receiver (PHY or MAC) samples the input signals only every 10 cycles in mode.

Limitations There is no signal that defines whether the interface is in full or half duplex mode, but both the MAC and the PHY need to agree. This must instead be communicated over the serial MDIO/MDC interface. There is also no signal which defines whether the interface is in 10 or mode, so this must also be handled using the MDIO/MDC interface. Version 1.2 of the RMII Consortium specification states that its MDIO/MDC interface is identical to that specified for MII in IEEE 802.3u. Current revisions of IEEE 802.3 specify a standard MDIO/MDC mechanism for negotiating and configuring the link's speed and duplex mode, but it is possible that older PHY devices might have been designed against obsolete versions of the standard, and may therefore use proprietary methods to set speed and duplex.

The lack of the RX_ER signal, which is not connected on some MACs (such as multiport switches), is dealt with by data replacement on some PHYs to invalidate the CRC. The missing COL signal is derived from AND-ing together the TX_EN and the decoded CRS signal from the CRS_DV line in half-duplex mode. This means a slight modification of the definition of CRS: On MII, CRS is asserted for both Rx and Tx frames; on RMII, only for Rx frames. This has the consequence that on RMII, the two error conditions no carrier and lost carrier cannot be detected, and it is difficult or impossible to support shared media such as 10BASE2 or 10BASE5.

Since the RMII standard neglected to stipulate that TX_EN should only be sampled on alternate clock cycles, it is not symmetric with CRS_DV and two RMII PHY devices cannot be connected back to back to form a repeater; this is possible, however, with the National DP83848, which supplies the decoded RX_DV as a supplemental signal in RMII mode.AN-1405 schematic

Signal levels TTL logic levels are used for or logic. Input high threshold is and low is . The specification states that inputs should be tolerant; however, some popular chips with RMII interfaces are not tolerant. Newer devices may support and logic.

The RMII signals are treated as lumped signals rather than transmission lines. However, the IEEE version of the related MII standard specifies trace impedance.AN-1469 datasheet National recommends running traces with series termination resistors for either MII or RMII mode to reduce reflections. National also suggests that traces be kept under long and matched within on length to minimize skew.

Gigabit media-independent interface