The PlayStation 2 technical specifications describe the various components of the PlayStation 2 (PS2) video game console.

Overview The sixth-generation hardware of the PlayStation 2 video game console consists of various components. At the heart of the console's configuration is its central processing unit (CPU), a custom RISC processor known as the Emotion Engine which operates at 294.912 MHz (299 MHz in later consoles). The CPU heavily relies on its integration with two vector processing units, known as VPU0 and VPU1, the Graphics Synthesizer, and a floating-point unit (FPU) in order to render 3D graphics. Other components, such as the system's DVD-ROM optical drive and DualShock 2 controller, provide the software and user control input.

PlayStation 2 software is distributed on CD-ROM and DVD-ROM. In addition, the console can play audio CDs and DVD movies, and is backwards compatible with original PlayStation games. This is accomplished through the inclusion of the original PlayStation's CPU which also serves as the PS2's I/O processor, clocked at 36.864 MHz in PS2 mode. The PS2 also supports full functionality with the original PlayStation memory cards and controllers. The PS2's DualShock 2 controller is an upgraded version of the PlayStation's DualShock with analog face, shoulder and D-pad buttons replacing the digital buttons of the original. Like its predecessor, the DualShock 2 controller features force feedback technology.

The standard PlayStation 2 memory card has an 8 MB capacity and uses Sony's MagicGate encryption. This requirement prevented the production of memory cards by third parties who did not purchase a MagicGate license. Memory cards without encryption can be used to store PlayStation game saves, but PlayStation games would be unable to read from or write to the card such a card could only be used as a backup. There are a variety of non-Sony manufactured memory cards available for the PlayStation 2, allowing for a larger memory capacity than the standard 8 MB. However their use is unsupported and compatibility is not guaranteed. These memory cards can have up to 128 MB storage space.

The console also features USB and IEEE 1394 expansion ports. Compatibility with USB and IEEE 1394 devices is dependent on the software supporting the device. For example, the PS2 BIOS will not boot an ISO image from a USB flash drive or operate a USB printer, as the machine's operating system does not include this functionality. By contrast, Gran Turismo 4 and Tourist Trophy are programmed to save screenshots to a USB mass storage device and print images on certain USB printers. A PlayStation 2 HDD can be installed via the expansion bay in the back of the console, and was required to play certain games, notably the popular Final Fantasy XI.

Central processing unit

CPU: MIPS III R5900-based "Emotion Engine", clocked at 294.912 MHz (299 MHz on newer versions), with 128-bit SIMD capabilitiesJohn L. Hennessy and David A. Patterson. "Computer Architecture: A Quantitative Approach, Third Edition". Keith Diefendorff. "Sony's Emotionally Charged Chip". Microprocessor Report, Volume 13, Number 5, April 19, 1999. Microdesign Resources. 250-nm CMOS manufacturing (ending with 65-nm CMOS), 13.5 million transistors, 225 mm2 die size, 15 W dissipation (combined EE+GS in SCPH-7500x and later SCPH-7000x): 86 mm2, 53.5 million transistors)Sony Interactive Entertainment sie.com (combined EE+RDRAM+DRAM in SCPH-7900x ended with 65 nm CMOS design) CPU core: MIPS R5900 (COP0), 64-bit, little endian (mipsel). CPU is a superscalar, in-order execution 2-issue design with 6-stage long integer pipelines, 32 32-bit GPR registers, 32 128-bit SIMD linear scalar registers, two 64-bit integer ALUs, 128-bit load-store unit (LSU) and a branch execution unit (BXU). Instruction set: MIPS III, MIPS IV subset with Sony's proprietary 107 vector SIMD multimedia instructions (MMI). The custom instruction set was implemented by grouping the two 64-bit integer ALUs. 32-bit FPU coprocessor (COP1) with 6-stage long pipeline (floating point multiply accumulator × 1, floating point divider × 1). FPU is not IEEE compliant. Two 32-bit VLIW-SIMD vector units at 294.912 MHz: VPU0 and VPU1 (floating point multiply accumulator × 9, floating point divider × 1) each VPU contains a vector unit (VU), instruction cache, data cache and interface unit. Each vector unit also has upper execution unit containing 4 × FMAC and lower execution unit containing FDIV, integer ALU, load-store unit, branch logic, 16 16-bit integer registers and 32 128-bit floating point registers. VPU1 has an additional EFU unit. VPU0 (COP2; FMAC × 4, FDIV × 1) is tightly coupled with the main CPU and is typically used for polygon and geometry transformations (under parallel or serial connection), physics and other gameplay related tasks VPU1 (Elementary Functional Unit, EFU; FMAC × 5, FDIV × 2) operates independently controlled by microcode, parallel to the CPU core, is typically used for polygon and geometry transformations, clipping, culling, lighting and other visual based calculations (texture matrix includes processing of UV & STQ coordinates) See bits on ps2's TnL & data setup. Also, look to pages 25 & 26 for a comparison of the ps2 to a PC architecture & memory setup, showing ps2 is based more around fast streaming of assets, as well as page 42 for a simple FSAA example. Parallel: results of VU0/FPU sent as another display list via MFIFO (for e.g. complex characters/vehicles/etc.) Serial: results of VU0/FPU sent to VU1 (via 3 methods) and can act as an optional geometry pre-processor that does all base work to update the scene every frame (for e.g. general transformations of world space relating to gameplay, such as boning and animation, physics and general motion) Image Processing Unit (IPU): MPEG-2 compressed image macroblock layer decoder allowing playback of DVDs and game FMV. It also allowed vector quantization for 2D graphics data. Memory management unit (MMU), RDRAM controller and DMA controller: handle memory access within the system Cache memory: 16 KB instruction cache, 8 KB data cache and 16 KB scratchpad (ScrP) data cache Scratchpad (SPR) is extended area of memory visible to the EE CPU. This extended memory provides 16 kilobytes of fast RAM available to be used by the application. Scratchpad memory can be used to store temporary data that is waiting to be sent via DMA or for any other temporary storage that the programmer can define.

Interfaces I/O processor interconnection: remote procedure call over a serial link, DMA controller for bulk transfer Main RDRAM memory bus. Bandwidth: 3.2 GB/s Graphics interface (GIF), DMA channel that connects the EE CPU to the GS ("Graphics Synthesizer") co-processor. To draw something to the screen, one must send, using 1 of 3 data paths, render commands & assets to the GS via the GIF channel: 64-bit, 150 MHz bus, maximum theoretical bandwidth of 1.2 GB/s. Display lists generated by CPU/VPU0 and VPU1 are sent to the GIF, which prioritizes them before dispatching them to the Graphics Synthesizer for rendering. Vector Unit Interface (VIF), consists of two DMA channels VIF0 for VPU0 and VIF1 for VPU1. Vector units and the main CPU communicate via VIF DMA channels. SIF – Serial Interface or Subsystem Interface which consists of 3 DMA channels: Subsystem Interface 0 (SIF0) and Subsystem Interface 1 (SIF1), used for communication between the EE main CPU and IOP co-processor. These are serial DMA channels where both CPUs can send commands and establish communication through an RPC protocol. Subsystem Interface 2 (SIF2), used for backwards compatibility with PS1 games and debugging.

Performance Floating point performance: 6.2 GFLOPS (single precision 32-bit floating point) FPU 0.64 GFLOPS VU0 2.44 GFLOPS VU1 3.08 GFLOPS (Including internal 0.64 GFLOPS EFU) Tri-strip geometric transformation (VU0+VU1): 150 million vertices per second 3D CG geometric transformation with raw 3D perspective operations (VU0+VU1): 66–80+ million vertices per second 3D CG geometric transformations at peak bones/movements/effects (textures)/lights (VU0+VU1, parallel or series): 15–20 million vertices per secondMalice PS2 Q&A See second question.Coding Secrets/Game Hut See Coding Secrets video on PS2's poly count and particle effects. Lighting: 38 million polygons/second Fog: 36 million polygons/second Curved surface generation (Bézier): 16 million polygons/second Image processing performance: 150 million pixels/second Actual real-world polygons (per frame): range of 500–600k at 30FPS, 250–300k at 60FPS Instructions per second: 6,000 MIPS (million instructions per second)

System memory Overall memory: 40 MB (42 MB after revision of system's IOP) Main memory: 32 MB PC800 32-bit dual-channel (2x 16-bit) RDRAM (Direct Rambus DRAM) @ 400 MHz, 3.2 GB/s peak bandwidth Stores all aspects & assets of an application or game's level, for fetching the right data at the right time, with assets being streamed to their appropriate destinations, when needed, a level's geometry, for instance, to either vector unit, via each unit's VIF, and textures to the GS, the system's GPU, via the GIFReaching for the Limits of PS2 Performance See pages 15 & 18, also, for an example of the default setup including sending textures, stored into main RAM at load up, to the GS, via the GIF.PS2 Optimizations See pages 11-13 about texture syncing & transfer methods, an example of the PS2's setup. Also, see pg.29 for fill-rate for 4 passes, per second, likely at the standard PAL or NTSC rates of 50 Hz or 60 Hz, along with more evidence about using full-screen passes to implement bump mapping, with an example for alternative fogging being shown on pg.31. Video memory: 4 MB of 2560-bit DRAM @ 150 MHz, 48 GB/sec peak bandwidth Stores temporal work or drawing buffers for drawing operations & mapping procedures; main memory, again, pre-storing all aspects & assets of a level, streaming only what that part of the frame needs processed & drawn at a time to the GIF, accumulating a single frame in small, very quick doses, bit by bit, using the video memory's buffers & high bandwidth, along the transfer bus speeds providedMDK2 Armageddon Chat Transcript "DavidBioWare What we've found since then is that the PS2 has enough bus bandwidth to transfer each texture from main memory to video memory as it's needed. That's on the order to 100s of Mb per second. We hadn't anticipated that the PS2 had that kind of brute horsepower on its bus. No other machine I've used does, including any PC or the Dreamcast. We had to reorient our thinking after that. :) So now we have almost more texture memory than we know what to do with." IOP memory: 2 MB of 32-bit EDO-RAM @ 37.5 MHz, 150 MB/sec peak bandwidthSony's Emotionally Charged Chip See pages 1, 2 & 4 Handles communication between external peripherals or devices & the hardware, also helping transfer data to the SPU2, the system's sound processing unit, via the same bus, its 32-bit bus being shared between the SPU2, optical drive, USB ports and moreIntroducing PS2 to PC programmers See pg.10 for IOP/SPU2 block Updated to 4 MB SDRAM as of revision to SCPH-7500x model systems Sound memory: 2 MB of 32-bit EDO-RAM @ 37.5 MHz Separate memory that shares the same local 32-bit bus for the IOP, thus using the same 150 Mbit/s bandwidth

Graphics processing unit

Parallel rendering processor with embedded DRAM "Graphics Synthesizer" (GS) clocked at 147.456 MHz 279 mm2 die (combined EE+GS in SCPH-7500x: 86 mm2, 53.5 million transistors) (GS in SCPH-7900x ended with 90 nm CMOS design) Dedicated connection from and to EE and VU1 via GIF Programmable CRT controller (PCRTC) for output Video output resolution: Variable from 256×224 to 2048×1024 NTSC (interleaved/progressive scan): 256 x 448/224, 320 x 448/224, 384 x 448/224, 512 x 448/224, 640 x 448/224 or 704 x 448/224