Electronic systems’ power consumption has been a real challenge for Hardware and Software designers as well as users especially in portable devices like cell phones and laptop computers. Power consumption also has been an issue for many industries that use computer systems heavily such as Internet service providers using servers or companies with many employees using computers and other computational devices. Many different approaches (during design of HW, SW or real-time estimation) have been discovered by researchers to estimate power consumption efficiently. This survey paper focuses on the different methods where power consumption can be estimated or measured in real-time.

Measuring real time power dissipation is critical in thermal analysis of a new design of HW like processors (CPU) just as it is important for OS programmers writing process schedulers. Researchers discovered that knowing the real-time power consumption on a subsystem level like CPU, hard drives, memory and other devices can help power optimizations in applications such as storage encryption, virtualization, and application sandboxing, as well as application tradeoffs.

Different technologies have been discovered that can enable measuring power consumption in real-time. These technologies can be categorized into two main categories: direct measurement using subsystem power sensors and meters or indirect estimation based on provided information such as temperature or performance counters.

Real-Time power management can be used to optimize the system or subsystems to minimize the energy consumption which may, for example, extend the battery lifetime of mobile devices or result in energy savings for Internet companies operating with many computer servers.

Indirect Power measurement

Indirect power measurement such as using a CPU performance monitoring unit (PMU), or performance counters to estimate run-time CPU and memory power consumption are widely used for their low cost.

Performance counters

Hardware performance counters (HPCs) are a set of special purpose registers built into modern microprocessors to store the counts of hardware-related activities for hardware and software related events. Different models of processors have limited numbers of hardware counters with different events that will satisfy the CPU requirement. These performance counters are usually accurate and provide important detailed information about processor performance at the clock cycle granularity. Researchers were able to create different models that use the HPCs event to estimate the system power consumption in real-time.

First-order, linear power estimation model using performance counters

The first-order linear model was developed by G. Contreras and M. Martonosi at Princeton University using Intel PXA255 processor to estimate CPU and memory power consumption. This is distinct from previous work that uses HPCs to estimate power because the Intel PXA255 processor power requirement was tighter and it offered fewer available performance events compared to mid and high-end processors. This method is also not tied to specific processor technology and HPCs layout for power estimation but rather can be used for any type of processor with HPCs.

This linear power model uses five performance events as follows: Instruction Executed, Data Dependencies, Instruction Cache Miss, Data TLB Misses, and Instruction TLB Misses. A linear model expression is derived (equation 1) as follows assuming a linear correlation between performance counters values and power consumption.

(1)

Where, are power weights and is a constant for processor power consumption during idle time.

One can also estimate power consumption of memory (external RAM) by tracking the performance events if they are available on the designed processor. PXA255 processor, for example, does not have direct performance events accounting for external RAM but Instruction Cache Miss, Data Cache Miss, and Number of Data Dependencies on processor can be used to estimate the memory power consumption. Again, a linear model is derived from the given information (equation 2) to estimate the memory power consumption.

(2)

Where, are power weights and is a power consumption constant during idle time.

The main challenging issue with this method is computing the power weights using a mathematical model (ordinary Least Squares Estimation) at different voltage/frequency points. These constant values in equations 1 and 2 are voltage and frequency depends and they must be computed during benchmark testing. After building such a table for the power weights parameters, then the table can be implemented in software or hardware to estimate the real-time power. The other challenge is in accessing HPCs; for example, in this case they are being read at the beginning of the main OS timer interrupt which requires a software modification. A software program can be written using the equations 1 and 2 and the estimated power weights derived from the table to estimate the power consumption at run-time. For equation 1 the program also needs 5 samples of HPCs but in this example the PXA255 processor can only sample 2 events at any given time therefore multiple code execution is required as well as aligning the data.

In summary, the main benefits of this approach are that it is easy to implement, low cost, and does not require special hardware modification. Software designers can benefit from this model by having a quick power estimate for their applications without any extra hardware requirement.

The main disadvantage of this method is that: real world processors are not perfect and this model does not account for non-linear relationships in those processors. Another issue is also the software overhead running on the processor that consumes power. This approach also does not provide detailed information about power consumption in each architectural functional unit so designers can not see the difference between each module by executing different parts of the software. This method can not be used by OS scheduler or software developers executing multi threaded programs because it needs to gather data by running benchmarks several times. This work is also good for single core processors but not multi-core processors.

Piece-wise linear power estimation model using performance counters

The piece-wise model was developed to estimate power consumption accurately using performance counters. This method was developed by K.Singh, M.Bhadauria at Cornell University and S.A.McKee at Chalmers University of Technology independently of program behavior for SPEC 2006, SPEC-OMP and NAS benchmark suits. This method was developed to analyze the effects of shared resources and temperature on power consumption for chip multiprocessors.

This method used 4 performance counters of AMD Phenom processor. The performance counters are as follows: : L2_CACHE_MISS: ALL, : RETRIED_UOPS, : RETIRED_MMX_AND_FP_INSTRUCTIONS: ALL, : DISPATCH_STALLS. These performance counters are architecturally specific to AMD Phenom and may be different for other processors. AMD allows collecting data from those four HPCs simultaneously. A microbenchmarks, which is a small program, attempts to collect data from the above selected HPCs. Collected data on each processor core are used in the following equation.

(3)

Where (4)

Equation 4 transformation can be linear, inverse, logarithmic, exponential, or square root; it depends on what makes the power predication more accurate. Piece wise linear function was chosen to analyze equation 4 from collected data because it will capture more detail about each processor core power. Finally, analyzing the collected HPCs data with piece wise linear method gives the detailed power consumption (for example, L2 cache misses has the highest contribution in power consumption versus L3).

The above method was used to schedule each AMD Phenom processor core in a defined power envelope. The processors core gets suspended when the core exceeds the available power envelope and it becomes available again when enough power becomes available.

There are some restrictions and issues with this method; for example, this method does not account for temperature effect. There is a direct relationship between temperature and total power consumption (because as temperature increases the leakage power goes up) that this model does not account for because AMD Phenom does not have per-core temperature sensors. A second disadvantage is that mictobenchmarks is not complete to get a better power estimate (for instance, it does not cover the DISPATCH_STALLS HPC). A more complete microbenchmark will cause timing issues. Future work needs to be done to incorporate thermal data into the model and thread scheduling strategies as well as to reduce frequency (DVFS) of each core versus suspending the core. This method only covers processors but there are other subsystems, like memory, and disks, that also need to be considered in total power.

This method is different from many other methods using performance counters because all the cores in multi core processors are considered, the performance counters being used do not individually have high effect with power consumption and it estimates the power consumption for each core that can be used for real time scheduling of each core to be under power envelope.

Adaptive power estimation model using performance counters

Most models like the above do not have the capability to measure power consumption at a component or subsystem level. DiPART (Disaggregated Power Analysis in Real Time) developed by Professor M. Srivastava, Y. Sun, and L. Wanner at University of California, Los Angeles enables this capability to estimate power consumption based on hardware performance counters and using only one power sensor for the whole system. Models are required to estimate power consumption based on performance counters. These models correlate the data for different performance counters with power consumption and static models like above examples (First-order and Piece-wise linear) have different estimation errors due to variations across identical hardware. DiPART is a solution to this problem because it is a self-adaptive model that can be calibrated once and be applied across different platforms.

The linear estimation model for DiPART requires a power sensor capable of acquiring dissipated power consumption and current measurement at run time. There are different embedded sensors like Atom-LEAP system or Qualcomm's Snapdragon Mobil Development Platforms that can do the job for DiPART. One single power sensor can be used to calibrate the subsystem level estimation model DiPART.

Total power of the system is the summation of the power consumption by each subsystem shown in equation 5.

(5)

For each subsystem, power performance counters are being used. For CPU power, ten performance counters are required as follows: Task counts, Context Switch counts, CPU Migration counts, Page Fault counts, Cycles counts, Instruction counts, Branches counts, Cache Refer counts, and Cache Miss Counts. Then a linear model is used to compute the total power of CPU and coefficient values are computed with a liner regression algorithm using performance counter data and monitored power consumption data.

(6)

The above performance counters can also be used for RAM power consumption model and the memory coefficient vector and the constant value is also computed during training phase with performance counter data and monitored power consumption data.

(7)

Disk power consumption model is based on input counter and output counter correlated with Input/Output events counters.

The same approach is taken as for CPU and RAM to estimate the coefficient and constant for disk power during training phase.

(8)