The IEEE/ACM International Symposium on Microarchitecture® (MICRO) is an annual academic conference on microarchitecture, generally viewed as the top-tier academic conference on computer architecture. It is not to be confused with a micro-conference. Particularly within the domains of microarchitecture and Code generation (compiler), MICRO is unrivaled and esteemed as the premier forum. Association for Computing Machinery's Special Interest Group on Microarchitecture (ACM SIGMICRO) and Institute of Electrical and Electronics Engineers Computer Society are technical sponsors.
MICRO Hall of Fame provides a list of the most prolific authors at the ISCA conference, spanning contributions starting from the first ISCA conference in 1973.
Events Event Year Location MICRO-1 1968 Bedford, Massachusetts, United States MICRO-2 1969 Phoenix, Arizona, United States MICRO-3 1970 Buffalo, New York, United States MICRO-4 1971 Santa Cruz, California, United States MICRO-5 1972 Champaign–Urbana, Illinois, United States MICRO-6 1973 College Park, Maryland, United States MICRO-7 1974 Palo Alto, California, United States MICRO-8 1975 Chicago, Illinois, United States MICRO-9 1976 New Orleans, Louisiana, United States MICRO-10 1977 Niagara Falls, New York, United States MICRO-11 1978 Asilomar (Pacific Grove), California, United States MICRO-12 1979 Hershey, Pennsylvania, United States MICRO-13 1980 Colorado Springs, Colorado, United States MICRO-14 1981 Chatham (Cape Cod), Massachusetts, United States MICRO-15 1982 Palo Alto, California, United States MICRO-16 1983 Downingtown, Pennsylvania, United States MICRO-17 1984 New Orleans, Louisiana, United States MICRO-18 1985 Pacific Grove (Asilomar), California, United States MICRO-19 1986 New York, New York, United States MICRO-20 1987 Colorado Springs, Colorado, United States MICRO-21 1988 San Diego, California, United States MICRO-22 1989 Dublin, Ireland MICRO-23 1990 Orlando, Florida, United States MICRO-24 1991 Albuquerque, New Mexico, United States MICRO-25 1992 Portland, Oregon, United States MICRO-26 1993 Austin, Texas, United States MICRO-27 1994 San Jose, California, United States MICRO-28 1995 Ann Arbor, Michigan, United States MICRO-29 1996 Paris, France MICRO-30 1997 Research Triangle Park, North Carolina, United States MICRO-31 1998 Dallas, Texas, United States MICRO-32 1999 Haifa, Israel MICRO-33 2000 Monterey, California, United States MICRO-34 2001 Austin, Texas, United States MICRO-35 2002 Istanbul, Turkey MICRO-36 2003 San Diego, California, United States MICRO-37 2004 Portland, Oregon, United States MICRO-38 2005 Barcelona, Spain MICRO-39 2006 Orlando, Florida, United States MICRO-40 2007 Chicago, Illinois, United States MICRO-41 2008 Lake Como, Italy MICRO-42 2009 New York, New York, United States MICRO-43 2010 Atlanta, Georgia, United States MICRO-44 2011 Porto Alegre, Brazil MICRO-45 2012 Vancouver, British Columbia, Canada MICRO-46 2013 Davis, California, United States MICRO-47 2014 Cambridge, United Kingdom MICRO-48 2015 Waikiki (Honolulu), Hawaii, United States MICRO-49 2016 Taipei, Taiwan MICRO-50 2017 Boston, Massachusetts, United States MICRO-51 2018 Fukuoka, Japan MICRO-52 2019 Columbus, Ohio, United States MICRO-53 2020 Athens (online), Greece MICRO-54 2021 Athens (online), Greece MICRO-55 2022 Chicago, Illinois, United States MICRO-56 2023 Toronto, Ontario, Canada MICRO-57 2024 Austin, Texas, United States MICRO-58 2025 Seoul, South Korea MICRO-59 2026 Athens, Greece
MICRO Test of Time (ToT) Award The SIGMICRO Test of Time (ToT) Award recognizes influential papers from prior editions of the International Symposium on Microarchitecture (MICRO). It was first awarded in 2014 (a special inaugural year recognizing 10 papers from 1968–1992) and has since been awarded annually, typically to papers published years prior to the award year.
Recent and past recipients 2024 (for MICRO 2006): Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches — Moinuddin K. Qureshi; Yale N. Patt. 2023 (for MICRO 2003): Orion: A Power-Performance Simulator for Interconnection Networks — Hang-Sheng Wang; Xinping Zhu; Li-Shiuan Peh; Sharad Malik. 2022 (for MICRO 2003): A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor — Shubhendu S. Mukherjee; Christopher T. Weaver; Joel S. Emer; Steven K. Reinhardt; Todd M. Austin. 2022 (for MICRO 2003): Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data — Canturk Isci; Margaret Martonosi. 2021 (for MICRO 2003): Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation — Dan Ernst; Nam Sung Kim; Shidhartha Das; Sanjay Pant; Rajeev R. Rao; Toan Pham; Conrad H. Ziesler; David T. Blaauw; Todd M. Austin; Krisztián Flautner; Trevor N. Mudge. 2021 (for MICRO 2003): Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction — Rakesh Kumar; Keith I. Farkas; Norman P. Jouppi; Parthasarathy Ranganathan; Dean M. Tullsen. 2020 (for MICRO 2000): A Permutation-Based Page Interleaving Scheme to Reduce Row-Buffer Conflicts and Exploit Data Locality — Zhao Zhang; Zhichun Zhu; Xiaodong Zhang. 2020 (for MICRO 1999): Fetch Directed Instruction Prefetching — Glenn Reinman; Brad Calder; Todd M. Austin. 2020 (for MICRO 1998): A Dynamic Multithreading Processor — Haitham Akkary; Michael A. Driscoll. 2019 (for MICRO 2001): Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution — Ravi Rajwar; James R. Goodman. 2019 (for MICRO 1999): Selective Cache Ways: On-Demand Cache Resource Allocation — David H. Albonesi. 2018 (for MICRO 1999): DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design — Todd M. Austin. 2018 (for MICRO 1996): Assigning Confidence to Conditional Branch Predictions — Erik Jacobsen; Eric Rotenberg; James E. Smith. 2018 (for MICRO 1996): Efficient Path Profiling — Thomas Ball; James R. Larus. 2017 (for MICRO 1996): Exceeding the Dataflow Limit Via Value Prediction — Mikko H. Lipasti; John Paul Shen. 2016 (for MICRO 1994): Iterative Modulo Scheduling: An Algorithm for Software Pipelining Loops — B. Ramakrishna Rau. 2015 (for MICRO 1996): Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching — Eric Rotenberg; Steve Bennett; James E. Smith. 2014 (inaugural set of 10 papers from 1968–1992).
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