The MCST R500S () is a 32-bit system-on-a-chip, developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC.
MCST R500S Highlights implements the SPARC V8 instruction set architecture (ISA) dual-core the two cores can work in redundancy to increase reliability of the system. core specifications: in-order, single-issue 5-stage integer pipeline 7-stage floating-point pipeline 16 KB L1 instruction cache 32 KB L1 data cache shared 512KB L2 cache integrated controllers: memory PCI RDMA (to connect with other MCST R500S) MSI (Mbus and SBus) EBus PS/2 Ethernet 100 SCSI-2 RS-232 500 МHz clock rate 130 nm process die size 100 mm2 ~45 million transistors power consumption 5W
References "https://web.archive.org/web/20151101211823/http://www.mcst.ru/b_18-19.shtml" (In Russian)