The Motorola 68000 series (also known as 680x0, m68000, m68k, or 68k) is a family of 32-bit complex instruction set computer (CISC) microprocessors. During the 1980s and early 1990s, they were popular in personal computers and workstations and were the primary competitors of Intel's x86 microprocessors.
The 680x0 series were best known as the processors used in the early Apple Macintosh, the Sharp X68000, the Commodore Amiga, the Sinclair QL, the Atari ST and Falcon, the Atari Jaguar, the Sega Genesis (Mega Drive) and Sega CD, the Philips CD-i, the Capcom System I (Arcade), the AT&T UNIX PC, the Tandy Model 16/16B/6000, the Sun Microsystems Sun-1, Sun-2 and Sun-3, the NeXT Computer, NeXTcube, NeXTstation, and NeXTcube Turbo, early Silicon Graphics IRIS workstations, the Aesthedes, computers from MASSCOMP, the Texas Instruments TI-89/TI-92 calculators, the Palm Pilot (all models running Palm OS 4.x or earlier), the Control Data Corporation CDCNET Device Interface, the VTech Precomputer Unlimited and the Space Shuttle.
Motorola ceased development of the 680x0 series architecture in 1994 and replaced it with PowerPC, a RISC-based architecture developed in conjunction with IBM and Apple Computer as part of the AIM alliance. While no modern computers today use processors based on the 680x0 series, derivatives are still used in various embedded systems.
Family members Generation one (internally 16/32-bit, and produced with 8-, 16-, and 32-bit interfaces) 68000 68EC000 68SEC000 68HC000 68008 68010 68012 Generation two (internally fully 32-bit) 68020 68EC020 68030 68EC030 Generation three (pipelined) 68040 68EC040 68LC040 Generation four (superscalar) 68060 68EC060 68LC060 Others Freescale 683XX (CPU32 aka 68330, 68360 aka QUICC) Freescale ColdFire Freescale DragonBall Philips 68070 Apollo 68080 Notes
Improvement history 68010: Virtual memory support (restartable instructions) "Loop mode" for faster string and memory library primitives Multiply instruction uses 14 fewer clock ticks 2 GiB directly accessible memory (68012 variant)
68020: 32-bit address & arithmetic logic unit (ALU) Three stage pipeline Instruction cache of 256 bytes Unrestricted word and longword data access (see alignment) 8× multiprocessing ability Larger multiply (32×32 → 64 bits) and divide (64÷32 → 32 bits quotient and 32 bits remainder) instructions, and bit field manipulations Addressing modes added scaled indexing and another level of indirection Low cost, EC = 24-bit address
68030: Split instruction and data cache of 256 bytes each On-chip memory management unit (MMU) (68851) Low cost EC = No MMU Burst Memory Interface
68040: Instruction and data caches of 4 KB each Six stage pipeline On-chip floating-point unit (FPU) FPU lacks IEEE transcendental function ability FPU emulation works with 2E71M and later chip revisions Low cost LC = No FPU Low cost EC = No FPU or MMU
68060: Instruction and data caches of 8 KB each 10 stage pipeline Two cycle integer multiplication unit Branch prediction Dual instruction pipeline Instructions in the address generation unit (AGU) and thereby supply the result two cycles before the ALU Low cost LC = No FPU Low cost EC = No FPU or MMU
Feature map Year CPU Package Frequency (max) [in MHz] Address bus bits MMU FPU 1979 68000 , , , , , , 24 - - 68EC000 , 24 - - 1982 68008 , 8–16.67 20 or 22 - - 1982 68010 , , 24 68451 - 1982 68012 31 68451 - 1984 68020 32 68851 68881 68EC020 , 24 - - 1987 68030 (max ), 32 MMU 68881 68EC030 , 32 - 68881 1991 68040 , 32 MMU FPU 68LC040 , 32 MMU - 68EC040 , 32 - - 1994 68060 32 MMU FPU 68LC060 , 208-pin QFP 32 MMU - 68EC060 32 - -
Uses
The 680x0 line of processors has been used in a variety of systems, from high-end Texas Instruments calculators (the TI-89, TI-92, and Voyage 200 lines) to all of the members of the Palm Pilot series that run Palm OS 1.x to 4.x (OS 5.x is ARM-based), and even radiation-hardened versions in the critical control systems of the Space Shuttle.
The 680x0 family was well known for powering desktop computers and video game consoles such as the Macintosh 128K, Amiga, Sinclair QL, Atari ST, Genesis / Mega Drive, Neo Geo AES/Neo Geo CD, CDTV. They were the processors of choice in the 1980s for Unix workstations and servers such as AT&T's UNIX PC, Tandy's Model 16/16B/6000, Sun Microsystems' Sun-1, Sun-2, Sun-3, NeXT Computer, Silicon Graphics (SGI), and numerous others. The Saturn uses the 68000 for audio processing and other I/O tasks, while the Jaguar includes a 68000 intended for basic system control and input processing, but was frequently used for running game logic. Many arcade boards also use processors from the 680x0 family including those from Sega, Capcom, and SNK.
The first several versions of Adobe's PostScript interpreters were 68000-based. The 68000 in the Apple LaserWriter and LaserWriter Plus was clocked faster than the version used then in Macintosh computers. A fast 68030 in later PostScript interpreters, including the standard resolution LaserWriter IIntx, IIf and IIg (also 300 dpi), the higher resolution LaserWriter Pro 600 series (usually 600 dpi, but limited to 300 dpi with minimum RAM installed) and the very high resolution Linotronic imagesetters, the 200PS (1500+ dpi) and 300PS (2500+ dpi). Thereafter, Adobe generally preferred a RISC for its processor, as its competitors, with their PostScript clones, had already gone with RISCs, often an AMD 29000-series. The early 68000-based Adobe PostScript interpreters and their hardware were named for Cold War-era U.S. rockets and missiles: Atlas, Redstone, etc.
Microcontrollers derived from the 680x0 family have been used in a huge variety of applications. CPU32 and ColdFire microcontrollers have been manufactured in the millions as automotive engine controllers.
Many proprietary video editing systems also use processors from the 680x0 family including the MacroSystem Casablanca (1997), which was a black box with an easy-to-use graphic interface intended for the amateur and hobby videographer market. It is also worth noting its earlier, bigger and more professional counterpart, the "DraCo" (1995). The groundbreaking Quantel Paintbox series of early based 24-bit paint and effects system was originally released in 1981 and during its lifetime used nearly the entire range of processors from the 680x0 family (except the 68060, which was never implemented in its design). Another contender in the video arena, the Abekas 8150 DVE system, used the 68EC030, and the Play Trinity, later renamed Globecaster, uses several 68030s. The Bosch FGS-4000/4500 Video Graphics System manufactured by Robert Bosch Corporation, later BTS (1983), used a 68000 as its main processor; it drove several others to perform 3D animation in a computer that could easily apply Gouraud and Phong shading and ran a modified version of the Motorola VERSAdos operating system.
Architecture + Motorola 68000 series registers 31 ... 23 ... 15 ... 07 ... 00 (bit position) Data registers D0 Data 0 D1 Data 1 D2 Data 2 D3 Data 3 D4 Data 4 D5 Data 5 D6 Data 6 D7 Data 7 Address registers A0 Address 0 A1 Address 1 A2 Address 2 A3 Address 3 A4 Address 4 A5 Address 5 A6 Address 6 Stack pointers A7 / USP Stack Pointer (user) A7' / SSP Stack Pointer (supervisor) Program counter PC Program Counter Status Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position) T S M 0 I 0 0 0 X N Z V C SR
People who are familiar with the PDP-11 or VAX usually feel comfortable with the 68000 series. With the exception of the split of general-purpose registers into specialized data and address registers, the 68000 architecture is in many ways a 32-bit PDP-11.
It had a more orthogonal instruction set than those of many processors that came before (e.g., 8080) and after (e.g., x86). That is, it was typically possible to combine operations freely with operands, rather than being restricted to using certain addressing modes with certain instructions. This property made programming relatively easy for humans, and also made it easier to write code generators for compilers.
The 68000 series has eight 32-bit general-purpose data registers (D0-D7), and eight address registers (A0-A7). The last address register is the stack pointer, and assemblers accept the label SP as equivalent to A7.
In addition, it has a 16-bit status register. The upper 8 bits is the system byte, and modification of it is privileged. The lower 8 bits is the user byte, also known as the condition code register (CCR), and modification of it is not privileged. The 68000 comparison, arithmetic, and logic operations modify condition codes to record their results for use by later conditional jumps. The condition code bits are "zero" (Z), "carry" (C), "overflow" (V), "extend" (X), and "negative" (N). The "extend" (X) flag deserves special mention, because it is separate from the carry flag. This permits the extra bit from arithmetic, logic, and shift operations to be separated from the carry for flow-of-control and linkage.
While the 68000 had a "supervisor mode", it did not meet the Popek and Goldberg virtualization requirements due to the single instruction "MOVE from SR", which copies the status register to another register, being unprivileged but sensitive. In the Motorola 68010 and later, this was made privileged, to better support virtualization software.
The 68000 series instruction set can be divided into the following broad categories:
Load and store (MOVE) Arithmetic (ADD, SUB, MULS, MULU, DIVS, DIVU) Bit shifting (ASL, ASR, LSL, LSR) Bit rotation (ROR, ROL, ROXL, ROXR)
Logic operations (AND, OR, NOT, EOR) Type conversion (byte to word and vice versa) Conditional and unconditional branches (BRA, Bcc - BEQ, BNE, BHI, BLO, BMI, BPL, etc.) Subroutine invocation and return (BSR, RTS) Stack management (LINK, UNLK, PEA) Causing and responding to interrupts Exception handling There is no equivalent to the x86 CPUID instruction to determine what CPU or MMU or FPU is present.
The Motorola 68020 added some new instructions that include some minor improvements and extensions to the supervisor state, several instructions for software management of a multiprocessing system (which were removed in the 68060), some support for high-level languages which did not get used much (and was removed from future 680x0 processors), bigger multiply (32×32→64 bits) and divide (64÷32→32 bits quotient and 32 bits remainder) instructions, and bit field manipulations.
The standard addressing modes are:
Register direct Data register, e.g. "D0" Address register, e.g. "A0" Register indirect Simple address, e.g. (A0) Address with post-increment, e.g. (A0)+ Address with pre-decrement, e.g. −(A0) Address with a 16-bit signed offset, e.g. 16(A0) Register indirect with index register and 8-bit signed offset e.g. 8(A0,D0) or 8(A0,A1) For (A0)+ and −(A0), the actual increment or decrement value is dependent on the operand size: a byte access adjusts the address register by 1, a word by 2, and a long by 4. PC (program counter) relative with displacement Relative 16-bit signed offset, e.g. 16(PC). This mode was very useful for position-independent code. Relative with 8-bit signed offset with index, e.g. 8(PC,D2) Absolute memory location Either a number, e.g. "$4000", or a symbolic name translated by the assembler Most assemblers used the "$" symbol for hexadecimal, instead of "0x" or a trailing H. There were 16 and 32-bit versions of this addressing mode Immediate mode Data stored in the instruction, e.g. "#400" Quick immediate mode 3-bit unsigned (or 8-bit signed with moveq) with value stored in opcode In addq and subq, 0 is the equivalent to 8 e.g. moveq #0,d0 was quicker than clr.l d0 (though both made D0 equal to 0)
Plus: access to the status register, and, in later models, other special registers.