This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design. Keil also provides a somewhat newer summary of vendors of ARM based processors. ARM further provides a chart displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM core families.
Processors
Designed by ARM
Product family ARM architecture Processor Feature Cache (I / D), MMU Typical MIPS @ MHz Reference ARM1 ARMv1 ARM1 First implementation None ARM2 ARMv2 ARM2 ARMv2 added the MUL (multiply) instruction None 0.33 DMIPS/MHz ARM2aS ARMv2a ARM250 Integrated MEMC (MMU), graphics and I/O processor. ARMv2a added the SWP and SWPB (swap) instructions None, MEMC1a ARM3 First integrated memory cache 4 KB unified 0.50 DMIPS/MHz ARM6 ARMv3 ARM60 ARMv3 first to support 32-bit memory address space (previously 26-bit).ARMv3M first added long multiply instructions (32x32=64). None 10 MIPS @ 12 MHz ARM600 As ARM60, cache and coprocessor bus (for FPA10 floating-point unit) 4 KB unified 28 MIPS @ 33 MHz ARM610 As ARM60, cache, no coprocessor bus 4 KB unified 17 MIPS @ 20 MHz0.65 DMIPS/MHz ARM7 ARMv3 ARM700 coprocessor bus (for FPA11 floating-point unit) 8 KB unified 40 MHz ARM710 As ARM700, no coprocessor bus 8 KB unified 40 MHz ARM710a As ARM710, also used as core of ARM7100 8 KB unified 40 MHz0.68 DMIPS/MHz ARM7T ARMv4TARM7TDMI(-S) 3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM 26-bit addressing None 15 MIPS @ 16.8 MHz63 DMIPS @ 70 MHz ARM710T As ARM7TDMI, cache 8 KB unified, MMU 36 MIPS @ 40 MHz ARM720T As ARM7TDMI, cache 8 KB unified, MMU with FCSE (Fast Context Switch Extension) 60 MIPS @ 59.8 MHz ARM740T As ARM7TDMI, cacheMPU ARM7EJ ARMv5TEJ ARM7EJ-S 5-stage pipeline, Thumb, Jazelle DBX, enhanced DSP instructions None ARM8 ARMv4 ARM810 5-stage pipeline, static branch prediction, double-bandwidth memory 8 KB unified, MMU 84 MIPS @ 72 MHz1.16 DMIPS/MHz ARM9T ARMv4T ARM9TDMI 5-stage pipeline, ThumbNone ARM920T As ARM9TDMI, cache 16 KB / 16 KB, MMU with FCSE (Fast Context Switch Extension) 200 MIPS @ 180 MHzRegister 13, FCSE PID register ARM920T Technical Reference Manual ARM922T As ARM9TDMI, caches 8 KB / 8 KB, MMU ARM940T As ARM9TDMI, caches 4 KB / 4 KB, MPU ARM9E ARMv5TE ARM946E-S Thumb, enhanced DSP instructions, caches Variable, tightly coupled memories, MPU ARM966E-S Thumb, enhanced DSP instructions No cache, TCMs ARM968E-S As ARM966E-S No cache, TCMs ARMv5TEJ ARM926EJ-S Thumb, Jazelle DBX, enhanced DSP instructions Variable, TCMs, MMU 220 MIPS @ 200 MHz ARMv5TE ARM996HS Clockless processor, as ARM966E-S No caches, TCMs, MPU ARM10E ARMv5TE ARM1020E 6-stage pipeline, Thumb, enhanced DSP instructions, (VFP) 32 KB / 32 KB, MMU ARM1022E As ARM1020E 16 KB / 16 KB, MMU ARMv5TEJ ARM1026EJ-S Thumb, Jazelle DBX, enhanced DSP instructions, (VFP) Variable, MMU or MPU ARM11 ARMv6 ARM1136J(F)-S 8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), enhanced DSP instructions, unaligned memory access Variable, MMU 740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz ARMv6T2 ARM1156T2(F)-S 9-stage pipeline, SIMD, Thumb-2, (VFP), enhanced DSP instructions Variable, MPU ARMv6Z ARM1176JZ(F)-S As ARM1136EJ(F)-S Variable, MMU + TrustZone 965 DMIPS @ 772 MHz ARMv6K ARM11MPCore As ARM1136EJ(F)-S, 1–4 core SMP Variable, MMU SecurCore ARMv6-M SC000 As Cortex-M0 0.9 DMIPS/MHz ARMv4T SC100 As ARM7TDMI ARMv7-M SC300 As Cortex-M3 1.25 DMIPS/MHz Cortex-M ARMv6-M Cortex-M0 Microcontroller profile, most Thumb + some Thumb-2, hardware multiply instruction (optional small), optional system timer, optional bit-banding memory Optional cache, no TCM, no MPU 0.84 DMIPS/MHz Cortex-M0+ Microcontroller profile, most Thumb + some Thumb-2, hardware multiply instruction (optional small), optional system timer, optional bit-banding memory Optional cache, no TCM, optional MPU with 8 regions 0.93 DMIPS/MHz Cortex-M1 Microcontroller profile, most Thumb + some Thumb-2, hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memory Optional cache, 0–1024 KB I-TCM, 0–1024 KB D-TCM, no MPU 136 DMIPS @ 170 MHz, (0.8 DMIPS/MHz FPGA-dependent) ARMv7-M Cortex-M3 Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memory Optional cache, no TCM, optional MPU with 8 regions 1.25 DMIPS/MHzARMv7E-M Cortex-M4 Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv4-SP single-precision FPU, hardware multiply and divide instructions, optional bit-banding memory Optional cache, no TCM, optional MPU with 8 regions 1.25 DMIPS/MHz (1.27 w/FPU) Cortex-M7 Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv5 single and double precision FPU, hardware multiply and divide instructions 0−64 KB I-cache, 0−64 KB D-cache, 0–16 MB I-TCM, 0–16 MB D-TCM (all these w/optional ECC), optional MPU with 8 or 16 regions 2.14 DMIPS/MHzARMv8-M Baseline Cortex-M23 Microcontroller profile, Thumb-1 (most), Thumb-2 (some), Divide, TrustZone Optional cache, no TCM, optional MPU with 16 regions 1.03 DMIPS/MHzARMv8-M Mainline Cortex-M33 Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processor Optional cache, no TCM, optional MPU with 16 regions 1.50 DMIPS/MHz Cortex-M35P Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processor Built-in cache (with option 2–16 KB), I-cache, no TCM, optional MPU with 16 regions 1.50 DMIPS/MHzARMv8.1-M Mainline Cortex-M52 1.60 DMIPS/MHz Cortex-M55 1.69 DMIPS/MHz Cortex-M85 3.13 DMIPS/MHz Cortex-R ARMv7-R Cortex-R4 Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic 0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 8/12 regions 1.67 DMIPS/MHz Cortex-R5 Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP) 0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 12/16 regions 1.67 DMIPS/MHz Cortex-R7 Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP 0–64 KB / 0–64 KB, ? of 0–128 KB TCM, opt. MPU with 16 regions 2.50 DMIPS/MHz Cortex-R8 TBD 0–64 KB / 0–64 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24 regions 2.50 DMIPS/MHzARMv8-R Cortex-R52 TBD 0–32 KB / 0–32 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24+24 regions 2.09 DMIPS/MHz Cortex-R52+ TBD 0–32 KB / 0–32 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24+24 regions 2.09 DMIPS/MHz Cortex-R82 TBD 16–128 KB /16–64 KB L1, 64K–1MB L2, 0.16–1 / 0.16–1 MB TCM,