MOS Technology Agnus

The MOS Technology "Agnus", usually called Agnus, is an integrated circuit in the custom chipset of the Amiga computer. The Agnus, Denise and Paula chips collectively formed the OCS and ECS chipsets.

The Agnus is the Address Generator Chip. Its main function, in chip area, is the RAM Address Generator and Register Address Encoder which handles all DMA addresses. The 8361 Agnus is made up of approximately 21000 transistors and contains DMA Channel Controllers. The Blitter and Copper are also contained here. Originally Agnus was fabricated in 5 μm manufacturing process like all OCS chipset.

Agnus features: Memory controller ("Chip" memory that can be accessed by the processor and the chipset) The Blitter, a bitmap manipulator. The Blitter is capable of copying blocks of display data, or any arbitrary data in the chip memory, at high speed with various raster operations as well as drawing pixel perfect lines and filling outlined polygons, while freeing the CPU for concurrent tasks. "Copper", a display synchronized co-processor 25 Direct Memory Access (DMA) channels, allowing graphics, sound and I/O to be used with minimal CPU intervention DRAM refresh controller Generates the system clock from the 28 MHz oscillator Video timing

Agnus was replaced by Alice in the Amiga 4000 and Amiga 1200 when the AGA chipset was introduced in 1992.

Chips by capability

OCS Agnus which can address up to 512 KB of Chip RAM (PLCC versions add 512 KB of pseudo-fast RAM) 8361 (DIP) - Amiga 1000 (NTSC); Amiga 2000 model A (NTSC) 8367 (DIP) - Amiga 1000 (PAL); Amiga 2000 model A (PAL) 8370 (PLCC) - Amiga 500 to Rev 5.x (NTSC); Amiga 2000 model B to Rev 4.5 (NTSC) 8371 (PLCC) - Amiga 500 to Rev 5.x (PAL); Amiga 2000 model B to Rev 4.5 (PAL) ECS Agnus which can address up to 1 MB of Chip RAM 8372 - no data* 8372A - Amiga 500 from Rev 6 (NTSC/PAL); Amiga 2000 model B from Rev 6.0 to Rev 6.3 (NTSC/PAL); Commodore CDTV 8375 (318069-16 only) (PAL) - Amiga 500 from Rev 6 (PAL); Amiga 2000 model B from Rev 6.4 (PAL) 8375 (318069-17 only) (NTSC) - Amiga 500 from Rev 6 (NTSC); Amiga 2000 model B from Rev 6.4 (NTSC) ECS Agnus which can address up to 2 MB of Chip RAM 8372AB - Amiga 3000 from Rev 6.1 to Rev 8.9 (NTSC/PAL) 8372B - Amiga 3000 Rev 9 (NTSC/PAL) 8375 (PAL) - Amiga 500 Plus; Amiga 600 (PAL) 8375 (NTSC) - Amiga 600 (NTSC)

* Somewhere 8372A Agnus mentioned as simply "8372".

Chips by package 48-lead DIP Agnus (aka thin Agnus): 8361; 8367 84-contact PLCC Fat Agnus (named Fat Lady on most Amiga 2000 motherboards) 8370; 8371; 8372; 8372A; 8372AB; 8372B; 8375

NotesFat Agnus 1MB and Fat Agnus 2MB also known as Super Agnus; Super Fat Agnus; Fatter Agnus; Big Agnus; Big Fat Agnus.

DMA Channels Priority Name Count Cycles/Rasterline Chip Notes MPU 1 varying CPU A Blitter 4 varying Agnus (internal) yields 1/4 cycles to CPU when BLTPRI not active B Bitplane 6 80 Denise impairs sprite channels on severe overscan C Copper 1 varying Agnus (internal) D Audio 4 4 Paula E Sprites 8 16 Denise F Disk 1 3 Paula G Memory Refresh 1 4 - Reference: Amiga 500 plus Service Manual

Pinout

PLCC versions When replacing or upgrading chips, pinouts need to be taken care of. Types are just mentioned for reference; four-digit types and pinouts/usage are not consistent.

PinOCS/ECS ECSAGA (Alice) DescriptionA500/2000A3000A500+/600A4000/12008370/18372837583741RD13DRD13DRD13DRD13Data Bus 16 bit, bit 132RD12DRD12DRD12DRD12 ...3RD11DRD11DRD11DRD114RD10DRD10DRD10DRD105RD9DRD9DRD9DRD96RD8DRD8DRD8DRD87RD7DRD7DRD7DRD78RD6DRD6DRD6DRD69RD5DRD5DRD5DRD510RD4DRD4DRD4DRD411RD3DRD3DRD3DRD312RD2DRD2DRD2DRD213RD1DRD1DRD1DRD114RD0DRD0DRD0DRD0Data Bus 16 bit, bit 015VccVccVccVcc1 +5V ±5%16RST*_RESET_RESET/RESETGlobal RESETn, low active17INT3_INTR_INTR/INTR18DMALDMALDMALDMAL19BLS*_BLISS_BLISS/BLS20DBR*_BLIT_BLIT/DBR21RRW_WE_WE/WE22PRWR/WR/WR/W23RGEN*_REGEN_REGEN_REGEN24AS*_AS_ASNC225RAMEN*_RAMEN_RAMEN/RAMEN26RGA8RGA8RGA8RGA827RGA7RGA7RGA7RGA728RGA6RGA6RGA6RGA629RGA5RGA5RGA5RGA530RGA4RGA4RGA4RGA431RGA3RGA3RGA3RGA332RGA2RGA2RGA2RGA233RGA1RGA1RGA1RGA13428 MHz28 MHz28 MHzSCLK35XCLKA20A20A2036XCLKEN*_XCLKEN_CDAC14 MHz37CDAC*_CDAC7 MHz/CDAC387 MHz7 MHzCCKQ7 MHz39CCKQCCKQCCKCCKQ40CCKCCK14MCCK41TESTTESTGND/NTSC42VssVss1DRA0GND243MA0DRA0DRA1DRA0Memory address bus 9 bit, bit 0 (except 8375 which is bit 1)44MA1DRA1DRA2DRA1 ...45MA2DRA2DRA3DRA246MA3DRA3DRA4DRA347MA4DRA4DRA5DRA448MA5DRA5DRA6DRA549MA6DRA6DRA7DRA650MA7DRA7DRA8DRA751MA8DRA8_LDSDRA8Memory address bus 9 bit, bit 8 (except 8375 which is bit _LDS)52LDS*_LDS_UDSVcc253UDS*_UDS_CASLNC154CASL*_CASL_CASU/CAS55CASU*_CASUDRA9Vbb56RAS1*DRA9_RAS1DRA957RAS0*_RAS_RAS0/RAS58VssVss2GNDGND359A19A19A19A1960A1A1A1A161A2A2A2A262A3A3A3A363A4A4A4A464A5A5A5A565A6A6A6A666A7A7A7A767A8A8A8A868A9A9A9A969A10A10A10A1070A11A11A11A1171A12A12A12A1272A13A13A13A1373A14A14A14A1474A15A15A15A1575A16A16A16A1676A17A17A17A1777A18A18A18A1878LP*_LPEN_LPEN/LPEN79VSY*_VSYNC_VSYNC/VSYNC80CSY*_CSYNC_CSYNC/CSYNC81HSY*_HSYNC_HSYNC/HSYNC82VssVss3GNDGND1Ground, common on whole board83RD15DRD15DRD15DRD15Data Bus 16 bit, bit 1584RD14DRD14DRD14DRD14Data Bus 16 bit, bit 14 References: A500 Service Training, A3000 Service Manual, A500+ Service Manual, A1200 schematics

MOS Technology Agnus

Bron en licentie