In electronic instrumentation and signal processing, a time-to-digital converter (TDC) is a device that detects events and produces digital representations of the times they occurred. Depending on its purpose and design, a TDC may report the time of arrival of each event, the event duration, or the elapsed time between two events. Events of interest are indicated by signal pulses.
Various methods are used for time-to-digital conversion. Some methods provide nanosecond accuracy, whereas others are capable of picosecond accuracy. The method used for any particular application depends on the type of signal to be monitored, the maximum event rate, and other factors. An interpolating TDC is sometimes called a time counter (TC).
When a TDC is used to determine the elapsed time between two pulses (known as the start and stop pulse), measurement is started and stopped when the rising or falling edge of a signal pulse crosses a specific amplitude threshold. This pattern is seen in many physical experiments, like time-of-flight and lifetime measurements in atomic and high energy physics, experiments that involve laser ranging and electronic research involving the testing of integrated circuits and high-speed data transfer.
Application TDCs are used to timestamp events and measure time differences between events, especially where picosecond precision and high accuracy is required, such as the measurement of events in high energy physics experiments, where particles (e.g. electrons, photons, and ions) are detected.
Another application is cost-effective and non-mechanical water flow metering by measuring the time difference between ultrasound pulses that travel through the flow and arrive at different times depending on the flow speed and direction.
In an all-digital phase-locked loop (ADPLL), a TDC measures the phase shift and its result is used to adjust the digital controlled oscillator (DCO).
Coarse measurement
If the required time resolution is not high (nanosecond resolution?), then counters can be used to make the conversion.
Basic counter
In its simplest implementation, a TDC is a counter that increments every clock cycle. At any particular moment, the contents of the counter indicates the current time. When an event occurs, the counter's value is captured in an output register.
In this approach, the measurement is an integer number of clock cycles, so the measurement is quantized to a clock period. To get finer resolution, a faster clock is needed. The accuracy of the measurement depends upon the stability of the clock frequency.
Typically a TDC uses a crystal oscillator reference frequency to achieve good long term stability. High stability crystal oscillators are usually relatively low frequency, such as 10 MHz (or 100 ns resolution).For example, a Hewlett-Packard (now Agilent) 10811 crystal oven oscillator; http://www.hparchive.com/Manuals/HP-10811AB-Manual.pdf To obtain higher resolution, a phase-locked loop frequency multiplier is sometimes used to generate a faster clock. For example, the above crystal reference oscillator might be multiplied by 100 to get a clock rate of 1 GHz (1 ns resolution).
Counter technology High clock rates impose additional design constraints on the counter: if the clock period is short, it is difficult to update the count. Binary counters, for example, need a fast carry architecture because they essentially add one to the previous counter value. A solution is using a hybrid counter architecture. A Johnson counter, for example, is a fast non-binary counter. It can be used to count very quickly the low order count; a more conventional binary counter can be used to accumulate the high order count. The fast counter is sometime called a prescaler.
The speed of counters fabricated in CMOS-technology is limited by the capacitance between the gate and the channel and by the resistance of the channel and the signal traces. The product of both is the cut-off-frequency. Modern chip technology allows multiple metal layers and therefore coils with a large number of windings to be inserted into the chip. This allows designers to peak the device for a specific frequency, which may lie above the cut-off-frequency of the original transistor.
A peaked variant of the Johnson counter is the traveling-wave counter which also achieves sub-cycle resolution. Other methods to achieve sub-cycle resolution include analog-to-digital converters and vernier Johnson counters.
Measuring a time interval
In most situations, the user does not want to just capture an absolute time that an event occurs, but wants to measure a time interval, i.e the time between a start event and a stop event.
That can be done by measuring an arbitrary time of both the start and stop events and subtracting. The measurement can be off by two counts.
The subtraction can be avoided if the counter is held at zero until the start event, counts during the interval, and then stops counting after the stop event.
Coarse counters base on a reference clock with signals generated at a stable frequency . When the start signal is detected the counter starts counting clock signals and terminates counting after the stop signal is detected. The time interval between start and stop is then
with , the number of counts and , the period of the reference clock.
Statistical counter Since start, stop and clock signal are asynchronous, there is a uniform probability distribution of the start and stop signal-times between two subsequent clock pulses. This detuning of the start and stop signal from the clock pulses is called quantization error.
For a series of measurements on the same constant and asynchronous time interval one measures two different numbers of counted clock pulses and (see picture). These occur with probabilities
with the fractional part of . The value for the time interval is then obtained by
Measuring a time interval using a coarse counter with the averaging method described above is relatively time consuming because of the many repetitions that are needed to determine the probabilities and . In comparison to the other methods described later on, a coarse counter has a very limited resolution (1 ns in case of a 1 GHz reference clock), but satisfies with its theoretically unlimited measuring range.
Fine measurement
In contrast to the coarse counter in the previous section, fine measurement methods with much better accuracy (picosecond resolution?), but far smaller measuring range are presented here. Analogue methods like time interval stretching or double conversion as well as digital methods like tapped delay lines and the Vernier method are under examination. Though the analogue methods still obtain better accuracies, digital time interval measurement is often preferred due to its flexibility in integrated circuit technology and its robustness against external perturbations like temperature changes.
The counter implementation's accuracy is limited by the clock frequency. If time is measured by whole counts, then the resolution is limited to the clock period. For example, a 10 MHz clock has a resolution of 100 ns. To get resolution finer than a clock period, there are time interpolation circuits., entry for time interval counter. These circuits measure the fraction of a clock period: that is, the time between a clock event and the event being measured. The interpolation circuits often require a significant amount of time to perform their function; consequently, the TDC needs a quiet interval before the next measurement.
Ramp interpolator
When counting is not feasible because the clock rate would be too high, analog methods can be used. Analog methods are often used to measure intervals that are between 10 and 200 ns. These methods often use a capacitor that is charged during the interval being measured. Initially, the capacitor is discharged to zero volts. When the start event occurs, the capacitor is charged with a constant current I1; the constant current causes the voltage v on the capacitor to increase linearly with time. The rising voltage is called the fast ramp. When the stop event occurs, the charging current is stopped. The voltage on the capacitor v is directly proportional to the time interval T and can be measured with an analog-to-digital converter (ADC). The resolution of such a system is in the range of 1 to 10 ps.. Kalisz states that the Stanford Research Systems SR620 uses this method.
Although a separate ADC can be used, the ADC step is often integrated into the interpolator. A second constant current I2 is used to discharge the capacitor at a constant but much slower rate (the slow ramp). The slow ramp might be 1/1000 of the fast ramp. This discharge effectively "stretches" the time interval; stating, "Effectively, the interpolator magnifies the interpolation or uncertainty interval by the ratio of the charge and discharge currents." it will take 1000 times as long for the capacitor to discharge to zero volts. The stretched interval can be measured with a counter. The measurement is similar to a dual-slope analog converter.
The dual-slope conversion can take a long time: a thousand or so clock ticks in the scheme described above. That limits how often a measurement can be made (dead time). Resolution of 1 ps with a 100 MHz (10 ns) clock requires a stretch ratio of 10,000 and implies a conversion time of 150 μs. To decrease the conversion time, the interpolator circuit can be used twice in a residual interpolator technique. The fast ramp is used initially as above to determine the time. The slow ramp is only at 1/100. The slow ramp will cross zero at some time during the clock period. When the ramp crosses zero, the fast ramp is turned on again to measure the crossing time (tresidual). Consequently, the time can be determined to 1 part in 10,000.
Interpolators are often used with a stable system clock. The start event is asynchronous, but the stop event is a following clock. For convenience, imagine that the fast ramp rises exactly 1 volt during a 100 ns clock period. Assume the start event occurs at 67.3 ns after a clock pulse; the fast ramp integrator is triggered and starts rising. The asynchronous start event is also routed through a synchronizer that takes at least two clock pulses. By the next clock pulse, the ramp has risen to .327 V. By the second clock pulse, the ramp has risen to 1.327 V and the synchronizer reports the start event has been seen. The fast ramp is stopped and the slow ramp starts. The synchronizer output can be used to capture system time from a counter. After 1327 clocks, the slow ramp returns to its starting point, and interpolator knows that the event occurred 132.7 ns before the synchronizer reported.
The interpolator is actually more involved because there are synchronizer issues and current switching is not instantaneous. Also, the interpolator must calibrate the height of the ramp to a clock period. stating, "In practice, the current sources and other circuitry used to build the interpolators are subject to operational variations over temperature and time. The 5360A's interpolators were in a special insulated cavity and had several adjustments. The 5335A uses a self-calibration technique that is not affected by temperature and needs no adjustments."
Vernier
Vernier interpolator