Low-Power Double Data Rate (LPDDR) is a type of synchronous dynamic random-access memory (SDRAM) designed to use less power than conventional memory. It is commonly used in smartphones, tablet computers, and laptops, where reducing power consumption is important for battery life. For this reason, earlier versions of the technology were also known as Mobile DDR.
LPDDR differs from standard DDR SDRAM in both design and features, with changes that make it more suitable for mobile devices. Unlike DDR, which is typically installed in removable modules, LPDDR is usually soldered directly onto the device's motherboard to conserve space and improve efficiency. Although LPDDR uses a generational naming convention similar to that of DDR memory (such as LPDDR4 and DDR4), the two follow separate development standards, and the version numbers do not indicate that they share the same technologies. The LPDDR standard is developed and maintained by the JEDEC Solid State Technology Association.
Bus width In contrast with standard SDRAM, used in stationary devices and laptops and usually connected over a 64-bit wide memory bus, LPDDR also permits 16- or 32-bit wide channels.
The "E" and "X" versions mark enhanced versions of the specifications. They formalize overclocking the memory array by usually 33%.
As with standard SDRAM, most generations double the internal fetch size and external transfer speed, DDR4 and LPDDR5 being the exceptions.
Generations
+ Comparison of LPDDR SDRAM generations Gene-ration Releaseyear Chip Bus Voltage(V) Clock rate(MHz) Cycle time(ns) Pre-fetch Clock rate(MHz) Transfer rate(MT/s) Bandwidth(MB/s) 1 2006 200 2n 200 400 1 600 1.8 1E 266 266 533 2 132 2 2009 200 4n 400 800 3 200 2E 266 533 1067 4 268 32012200 8n80016004 800 3E 266106721338 532 42014200 16n1600320012 800 4X20172662133426717 068 520194003200640025 600 5X202166653331066742 668 6202590072001440057 600
LPDDR(1) The original low-power DDR (sometimes retroactively called LPDDR1), released in 2006 is a slightly modified form of DDR SDRAM, with several changes to reduce overall power consumption.
Most significantly, the supply voltage is reduced from 2.5 to 1.8 V. Additional savings come from temperature-compensated refresh (DRAM requires refresh less often at low temperatures), partial array self refresh, and a "deep power down" mode which sacrifices all memory contents. Additionally, chips are smaller, using less board space than their non-mobile equivalents. Samsung and Micron are two of the main providers of this technology, which is used in tablet and phone devices such as the iPhone 3GS, original iPad, Samsung Galaxy Tab 7.0 and Motorola Droid X., AnandTech (review), 23 December 2010, via Archive today.
LPDDR2
In 2009, the standards group JEDEC published JESD209-2, which defined a more dramatically revised low-power DDR interface. It is not compatible with either DDR1 or DDR2 SDRAM, but can accommodate any one of:
LPDDR2-S2: 2n prefetch memory (like DDR1), LPDDR2-S4: 4n prefetch memory (like DDR2), or LPDDR2-N: Non-volatile (NAND flash) memory.
Low-power states are similar to basic LPDDR, with some additional partial array refresh options.
Timing parameters are specified for LPDDR-200 to LPDDR-1066 (clock frequencies of 100 to 533 MHz).
Working at 1.2 V, LPDDR2 multiplexes the control and address lines onto a 10-bit double data rate CA bus. The commands are similar to those of normal SDRAM, except for the reassignment of the precharge and burst terminate opcodes:
+ LPDDR2/LPDDR3 command encoding Operation ↗ Rising clock ↗ ↘ Falling clock ↘ CA0() CA1() CA2() CA3 CA4 CA5 CA6 CA7 CA8 CA9 CA0() CA1() CA2() CA3 CA4 CA5 CA6 CA7 CA8 CA9 No operation — Precharge all banks — Precharge one bank — BA0 BA1 BA2 — Preactive (LPDDR2-N only) A30 A31 A32 BA0 BA1 BA2 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 Burst terminate — Read (AP=auto-precharge) reserved C1 C2 BA0 BA1 BA2 C3 C4 C5 C6 C7 C8 C9 C10 C11 Write (AP=auto-precharge) reserved C1 C2 BA0 BA1 BA2 C3 C4 C5 C6 C7 C8 C9 C10 C11 Activate (R0–14=Row address) R8 R9 R10 R11 R12 BA0 BA1 BA2 R0 R1 R2 R3 R4 R5 R6 R7 R13 R14 Activate (LPDDR2-N only) A15 A16 A17 A18 A19 BA0 BA1 BA2 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 Refresh all banks (LPDDR2-Sx only) — Refresh one bank (round-robin addr.) — Mode register read (MA0–7=addr.) MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 — Mode register write (OP0–7=data) MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7
Column address bit C0 is never transferred, and is assumed to be zero. Burst transfers thus always begin at even addresses.
LPDDR2 also has an active-low chip select (when high, everything is a NOP) and clock enable CKE signal, which operate like SDRAM. Also like SDRAM, the command sent on the cycle that CKE is first dropped selects the power-down state:
If the chip is active, it freezes in place. If the command is a NOP ( low or CA0–2 = HHH), the chip idles. If the command is a refresh command (CA0–2 = LLH), the chip enters the self-refresh state. If the command is a burst terminate (CA0–2 = HHL), the chip enters the deep power-down state. (A full reset sequence is required when leaving.)
The mode registers have been greatly expanded compared to conventional SDRAM, with an 8-bit address space, and the ability to read them back. Although smaller than a serial presence detect EEPROM, enough information is included to eliminate the need for one.
S2 devices smaller than 4 Gbit, and S4 devices smaller than 1 Gbit have only four banks. They ignore the BA2 signal, and do not support per-bank refresh.
Non-volatile memory devices do not use the refresh commands, and reassign the precharge command to transfer address bits A20 and up. The low-order bits (A19 and down) are transferred by a following Activate command. This transfers the selected row from the memory array to one of 4 or 8 (selected by the BA bits) row data buffers, where they can be read by a Read command. Unlike DRAM, the bank address bits are not part of the memory address; any address can be transferred to any row data buffer. A row data buffer may be from 32 to 4096 bytes long, depending on the type of memory. Rows larger than 32 bytes ignore some of the low-order address bits in the Activate command. Rows smaller than 4096 bytes ignore some of the high-order address bits in the Read command.
Non-volatile memory does not support the Write command to row data buffers. Rather, a series of control registers in a special address region support Read and Write commands, which can be used to erase and program the memory array.
LPDDR3 In May 2012, JEDEC published the JESD209-3 Low Power Memory Device Standard.JEDEC publishes LPDDR3 standard for low-power memory chips , Solid State Technology magazineJESD209-3 LPDDR3 Low Power Memory Device Standard, JEDEC Solid State Technology Association In comparison to LPDDR2, LPDDR3 offers a higher data rate, greater bandwidth and power efficiency, and higher memory density. LPDDR3 achieves a data rate of 1600 MT/s and utilizes key new technologies: write-leveling and command/address training,Want a quick and dirty overview of the new JEDEC LPDDR3 spec? EETimes serves it up , Denali Memory Report optional on-die termination (ODT), and low-I/O capacitance. LPDDR3 supports both package-on-package (PoP) and discrete packaging types.
The command encoding is identical to LPDDR2, using a 10-bit double data rate CA bus. However, the standard only specifies 8n-prefetch DRAM, and does not include the flash memory commands.
Products using LPDDR3 include the 2013 MacBook Air, iPhone 5S, iPhone 6, Nexus 10, Samsung Galaxy S4 (GT-I9500) and Microsoft Surface Pro 3 and 4.Inside the Samsung Galaxy S4 , Chipworks LPDDR3 went mainstream in 2013, running at 800 MHz DDR (1600 MT/s), offering bandwidth comparable to PC3-12800 notebook memory in 2011 (12.8 GB/s of bandwidth).Samsung LPDDR3 High-Performance Memory Enables Amazing Mobile Devices in 2013, 2014 - Bright Side of News To achieve this bandwidth, the controller must implement dual-channel memory. For example, this is the case for the Exynos 5 Dual and the 5 Octa.Samsung reveals eight-core mobile processor on EEtimes
LPDDR3E
An "enhanced" version of the specification called LPDDR3E increases the data rate to 2133 MT/s. Samsung Electronics introduced the first 4 gigabit 20 nm-class LPDDR3 modules capable of transmitting data at up to 2,133 MT/s, more than double the performance of the older LPDDR2 which is only capable of 800 MT/s.Now Producing Four Gigabit LPDDR3 Mobile DRAM, Using 20nm-class* Process Technology, Businesswire Various SoCs from various manufacturers also natively support 800 MHz LPDDR3 RAM. Such include the Snapdragon 600 and 800 from QualcommSnapdragon 800 Series and 600 Processors Unveiled , Qualcomm as well as some SoCs from the Exynos and Allwinner series.
LPDDR4 On 14 March 2012, JEDEC hosted a conference to explore how future mobile device requirements will drive upcoming standards like LPDDR4. On 30 December 2013, Samsung announced that it had developed the first 20 nm-class 8 gigabit (1 GB) LPDDR4 capable of transmitting data at 3,200 MT/s, thus providing 50 percent higher performance than the fastest LPDDR3 and consuming around 40 percent less energy at 1.1 volts. JESD79 DDR4 SDRAM Standard
On 25 August 2014, JEDEC published the JESD209-4 LPDDR4 Low Power Memory Device Standard. 'JEDEC Releases LPDDR4 Standard for Low Power Memory Devices', JEDEC Solid State Technology Association.
Significant changes include: Doubling of the interface speed, and numerous consequent electrical changes, including changing the I/O standard to low-voltage swing-terminated logic (LVSTL) Doubling of the internal prefetch size, and minimum transfer size Change from a 10-bit DDR command/address bus to a 6-bit SDR bus Change from one 32-bit wide bus to two independent 16-bit wide buses Self-refresh is enabled by dedicated commands, rather than being controlled by the CKE line
The standard defines SDRAM packages containing two independent 16-bit access channels, each connected to up to two dies per package. Each channel is 16 data bits wide, has its own control/address pins, and allows access to 8 banks of DRAM. Thus, the package may be connected in three ways: Data lines and control connected in parallel to a 16-bit data bus, and only chip selects connected independently per channel. To two halves of a 32-bit wide data bus, and the control lines in parallel, including chip select. To two independent 16-bit wide data buses
Each die provides 4, 6, 8, 12, or 16 gigabits of memory, half to each channel. Thus, each bank is one sixteenth the device size. This is organized into the appropriate number (16 K to 64 K) of 16384-bit (2048-byte) rows. Extension to 24 and 32 gigabits is planned, but it is not yet decided if this will be done by increasing the number of rows, their width, or the number of banks.
Larger packages providing double width (four channels) and up to four dies per pair of channels (8 dies total per package) are also defined.
Data is accessed in bursts of either 16 or 32 transfers (256 or 512 bits, 32 or 64 bytes, 8 or 16 cycles DDR). Bursts must begin on 64-bit boundaries.
Since the clock frequency is higher and the minimum burst length longer than earlier standards, control signals can be more highly multiplexed without the command/address bus becoming a bottleneck. LPDDR4 multiplexes the control and address lines onto a 6-bit single data rate CA bus. Commands require 2 clock cycles, and operations encoding an address (e.g., activate row, read or write column) require two commands. For example, to request a read from an idle chip requires four commands taking 8 clock cycles: Activate-1, Activate-2, Read, CAS-2.
The chip select line (CS) is active-high. The first cycle of a command is identified by chip select being high; it is low during the second cycle.