The PDP-11 architecture is a 16-bit CISC instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). It is implemented by central processing units (CPUs) and microprocessors used in PDP-11 minicomputers. It was in wide use during the 1970s, but was eventually overshadowed by the more powerful VAX architecture in the 1980s.
CPU registers
+ DEC PDP-11 registers 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position) Main registers R0 Register 0 R1 Register 1 R2 Register 2 R3 Register 3 R4 Register 4 R5 Register 5 Stack pointer R6 / SP Stack Pointer Program counter R7 / PC Program Counter Status flags CPU specific I T N Z V C Processor Status Word Floating Point Status
The CPU contains eight general-purpose 16-bit registers (R0 to R7). Register R7 is the program counter (PC). Although any register can be used as a stack pointer, R6 is the stack pointer (SP) used for hardware interrupts and traps. R5 is often used to point to the current procedure call frame. To speed up context switching, some PDP-11 models provide dual R0–R5 register sets. Kernel, Supervisor (where present), and User modes have separate memory maps, and also separate stack pointers (so that a user program cannot cause the system to malfunction by storing an invalid value in the stack pointer register).
Memory Data formats The smallest unit of addressable and writable memory is the 8-bit byte. Bytes can also be held in the lower half of registers R0 through R5.
16-bit words are stored little-endian with least significant bytes at the lower address. Words are always aligned to even memory addresses. Words can be held in registers R0 through R7.
32-bit double words in the Extended Instruction Set (EIS) can only be stored in register pairs with the higher word being stored in the lower-numbered register. Double words are used by the MUL, DIV, and ASHC instructions. Other 32-bit data are supported as extensions to the basic architecture: single-precision floating point in the Floating Instruction Set (FIS) and the instruction set for the floating-point processor option (FPP) for 11/45 and most subsequent models, and long data in the Commercial Instruction Set (CIS), are stored in more than one format, including an unusual middle-endian format sometimes referred to as "PDP-endian".
A 64-bit double-precision floating-point format is supported by the FPP option.
Memory management The PDP-11's 16-bit addresses can address 64 KB. By the time the PDP-11 yielded to the VAX, 8-bit bytes and hexadecimal notation were becoming standard in the industry; however, numeric values on the PDP-11 always use octal notation, and the amount of memory attached to a PDP-11 is always stated as a number of words. The basic logical address space is 32K words, but the high 4K of physical address space (addresses 160000 through 177777 in the absence of memory management) are not populated because input/output registers on the bus respond to addresses in that range. So originally, a fully expanded PDP-11 had 28K words, or 56 kbytes in modern terms.
The processor reserves low memory addresses for two-word vectors that give a program counter and processor status word with which to begin a service routine. When an I/O device interrupts a program, it places the address of its vector on the bus to indicate which service routine should take control. The lowest vectors are service routines to handle various types of trap. Traps occur on some program errors, such as an attempt to execute an undefined instruction; and also when the program executes an instruction such as BPT, EMT, IOT, or TRAP to request service from the operating system.
Memory expansion By 1975, PDP-11's 16-bit logical address space became an increasing limitation. Various techniques were used to work around it: Later-model PDP-11 processors include memory management to support virtual addressing. The physical address space was extended to 18 or 22 bits, hence allowing up to 256 KB or 4 MB of RAM. The logical address space (that is, the address space available at any moment without changing the memory mapping table) remains limited to 16 bits. Some models, beginning with the PDP-11/45, can be set to use 32K words (64 KB) as the "instruction space" for program code and a separate 32K words of "data space". Some operating systems—notably Unix since edition V7, and RSX11-M+—rely on this feature. Programming techniques, such as overlaying a block of stored instructions or data with another as needed, can conceal paging issues from the application programmer. For example, the Modula-2 compiler produces code under which the run-time system swaps 8 Kb pages into memory as individual procedures receive control.
Addressing modes Most instructions allocate six bits to specify an operand. Three bits select one of eight addressing modes, and three bits select a general register.
The encoding of the six bit operand addressing mode is as follows:
5320ModeRegister
In the following sections, each item includes an example of how the operand would be written in assembly language. Rn means one of the eight registers, written R0 through R7.
General register addressing modes The following eight modes can be applied to any general register. Their effects when applied to R6 (the stack pointer, SP) and R7 (the program counter, PC) are set out separately in the following sections. CodeNameExampleDescription0nRegisterRnThe operand is in Rn1nRegister deferred(Rn)Rn contains the address of the operand2nAutoincrement(Rn)+Rn contains the address of the operand, then increment Rn3nAutoincrement deferred@(Rn)+Rn contains the address of the address of the operand, then increment Rn by 24nAutodecrement−(Rn)Decrement Rn, then use the result as the address of the operand5nAutodecrement deferred@−(Rn)Decrement Rn by 2, then use the result as the address of the address of the operand6nIndexX(Rn)Rn+X is the address of the operand7nIndex deferred@X(Rn)Rn+X is the address of the address of the operand
In index and index deferred modes, X is a 16-bit value taken from a second word of the instruction. In double-operand instructions, both operands can use these modes. Such instructions are three words long.
Autoincrement and autodecrement operations on a register are by 1 in byte instructions, by 2 in word instructions, and by 2 whenever a deferred mode is used, since the quantity the register addresses is a (word) pointer.
Program counter addressing modes When R7 (the program counter) is specified, four of the addressing modes naturally yield useful effects: CodeNameExampleDescription27Immediate#nThe operand is the next word of the instruction37Absolute@#aThe address of the operand is the next word of the instruction67RelativeaThe address of the operand is the next word of the instruction added to the PC77Relative deferred@aThe address of the address of the operand is the next word of the instruction added to PC
The only common use of absolute mode, whose syntax combines immediate and deferred mode, is to specify input/output registers, as the registers for each device have specific memory addresses. Relative mode has a simpler syntax and is more typical for referring to program variables and jump destinations. A program that uses relative mode (and relative deferred mode) exclusively for internal references is position-independent; it contains no assumptions about its own location, so it can be loaded into an arbitrary memory location, or even moved, with no need for its addresses to be adjusted to reflect its location (relocated). In computing such addresses relative to the current location, the processor performs relocation on the fly.
Immediate and absolute modes are merely autoincrement and autoincrement deferred mode, respectively, applied to PC. When the auxiliary word is "in the instruction" as the above table says, the PC for the next instruction is automatically incremented past the auxiliary word. As PC always points to words, the autoincrement operation is always by 2.
Stack addressing modes R6, also written SP, is used as a hardware stack for traps and interrupts. A convention enforced by the set of modes the PDP-11 provides is that a stack grows downward—toward lower addresses—as items are pushed onto it. When a mode is applied to SP, or to any register the programmer elects to use as a software stack, the addressing modes have the following effects: CodeNameExampleDescription16Deferred(SP)The operand is on the top of the stack26Autoincrement(SP)+The operand is on the top of the stack, then pop it off36Autoincrement deferred@(SP)+A pointer to the operand is on top of the stack; pop the pointer off46Autodecrement −(SP)Push a value onto the stack66IndexedX(SP)The operand is X distance from the top of the stack76Indexed deferred@X(SP)A pointer to the operand is X distance from the top of the stack
Although software stacks can contain bytes, SP is always a stack of words. Autoincrement and autodecrement operations on SP are always by 2.
Instruction set The PDP-11 operates on bytes and words. Bytes are specified by a register number—identifying the register's low-order byte—or by a memory location. Words are specified by a register number or by the memory location of the low-order byte, which must be an even location. In most instructions that take operands, bit 15 is set to specify byte addressing, or clear to specify word addressing. In the lists in the following two sections, the assembly-language programmer appended B to the instruction symbol to specify a byte operation; for example, MOV became MOVB.
A few instructions, for example MARK and SOB, were not implemented on some PDP-11 models.
Double-operand instructions The high-order four bits specify the operation to be performed (with bit 15 generally selecting word versus byte addressing). Two groups of six bits specify the source operand addressing mode and the destination operand addressing mode, as defined above. This group of instructions takes up 75% of available opcodes.
1512119865320OpcodeSrcRegisterDestRegister
Opcode Mnemonic Operation01 MOV Move: Dest ← Src (MOVB to register sign-extends to bits 8-15)11 MOVB02 CMP Compare: Src − Dest12 CMPB03 BIT Bit test: Src ∧ Dest13 BITB04 BIC Bit clear: Dest ← Dest ∧ (-1 - Src)14 BICB05 BIS Bit set: Dest ← Dest ∨ Src15 BISB06 ADD Add: Dest ← Dest + Src16 SUB Subtract: Dest ← Dest − Src
The ADD and SUB instructions use word addressing, and have no byte-oriented variations.
Due to encoding limitations, some two-operand instructions utilize an addressing mode operand and a register operand:
159865320OpcodeRegSrc/DestRegister
Where a register pair is used (written below as "(Reg, Reg+1)", the first register contains the high-order portion of the operand and must be an even numbered register. The next higher numbered register contains the low-order portion of the operand (or the remainder). An exception is the multiply instruction; Reg may be odd, but if it is, the high 16 bits of the result are not stored. Opcode Mnemonic Operation070MUL Signed multiply: (Reg, Reg+1) ← Reg × Src071 DIV Signed divide: Compute (Reg, Reg+1) ÷ Src; Reg ← quotient; Reg+1 ← remainder072 ASH Arithmetic shift: if Src<5:0> < 0 then Reg ← Shift-right(Reg, -Src<5:0>) else Reg ← Shift-left(Reg, Src<5:0>)073 ASHC Arithmetic shift combined (32 bit): if Src<5:0> < 0 then (Reg, Reg+1) ← Shift-right((Reg, Reg+1), -Src<5:0>) else (Reg, Reg+1) ← Shift-left((Reg, Reg+1), Src<5:0>)074 XOR Exclusive or: Dest ← Dest ⊻ Reg
Single-operand instructions The high-order ten bits specify the operation to be performed, with bit 15 generally selecting byte versus word addressing. A single group of six bits specifies the operand as defined above.
1565320OpcodeSrc/DestRegister