The Alpha 21064 is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha (introduced as the Alpha AXP) instruction set architecture (ISA). It was introduced as the DECchip 21064 before it was renamed in 1994. The 21064 is also known by its code name, EV4. It was announced in February 1992 with volume availability in September 1992. The 21064 was the first commercial implementation of the Alpha ISA, and the first microprocessor from Digital to be available commercially. It was succeeded by a derivative, the Alpha 21064A in October 1993. This last version was replaced by the Alpha 21164 in 1995.
History The first Alpha processor was a test chip codenamed EV3. This test chip was fabricated using Digital's 1.0-micrometre (μm) CMOS-3 process. The test chip lacked a floating point unit and only had 1 KB caches. The test chip was used to confirm the operation of the aggressive circuit design techniques. The test chip, along with simulators and emulators, was also used to bring up firmware and the various operating systems that the company supported.
The production chip, codenamed EV4, was fabricated using Digital's 0.75 μm CMOS-4 process. Dirk Meyer and Edward McLellan were the micro-architects. Ed designed the issue logic while Dirk designed the other major blocks. Jim Montanaro led the circuit implementation. The EV3 was used in the Alpha Demonstration Unit (ADU), a multiprocessor system used by Digital to develop software for the Alpha platform before the availability of EV4 parts.
The 21064 was unveiled at the 39th International Solid-State Circuits Conference (ISSCC) in mid-February 1992. It was announced on 25 February 1992, with a 150 MHz sample introduced on the same day. It was priced at $3,375 in quantities of 100, $1,650 in quantities between 100 and 1,000, and $1,560 for quantities over 1,000. Volume shipments began in September 1992.
In early February 1993, the price of the 150 MHz version was reduced to $1,096 from $1,559 in quantities greater than 1,000.
On 25 February 1993, a 200 MHz was introduced, with sample kits available, priced at $3,495. In volume, it was priced at $1,231 per unit in quantities greater than 10,000. Volume orders were accepted in June 1993, with shipments in August 1993. The price of the 150 MHz version was reduced in response. The sample kit was reduced to $1,690 from $3,375, effective in April 1993; and in volume, it was reduced to $853 from $1,355 per unit in quantities greater than 10,000, effective in July 1993.
With the introduction of the Alpha 21066 and the Alpha 21068 on 10 September 1993, Digital adjusted the positioning of the existing 21064s and introduced a 166 MHz version priced at $499 per unit in quantities of 5,000. The price of the 150 MHz version was reduced to $455 per unit in quantities of 5,000.
On 6 June 1994, the price of the 200 MHz version was reduced by 31% to $544 to position it against the 60 MHz Pentium; and the 166 MHz version by 19% to $404 per unit in quantities of 5,000, effective on 3 July 1994.
DEC was the only manufacturer, with no second source. The Alpha 21064 was fabricated at Digital's Hudson, Massachusetts and South Queensferry, Scotland facilities.
Users The 21064 was mostly used in high-end computers such as workstations and servers. Users included:
Aspen Systems in its Alpine workstations Carrera Computers in its Hercules 150, Hercules 200, and Pantera II workstations Cray Research, which used the 150 MHz 21064 in its Cray T3D supercomputers Digital, in its DECpc AXP 150 entry-level workstations, DEC 2000 AXP entry-level servers, DEC 3000 AXP workstations and entry-level servers, DEC 4000 AXP mid-range servers and DEC 7000/10000 AXP high-end servers Encore Computer, in its Infinity R/T high-end real-time computer
Performance The 21064 was the highest performing microprocessor from when it was introduced until 1993, after International Business Machines (IBM) introduced the multi-chip POWER2. It remained the highest performing single-chip microprocessor until the 275 MHz 21064A was introduced in October 1993.Ryan 1994
Description The Alpha 21064 is a superpipelined dual-issue superscalar microprocessor that executes instructions in-order. It is capable of issuing up to two instructions every clock cycle to four functional units: an integer unit, a floating-point unit (FPU), an address unit, and a branch unit. The integer pipeline is seven stages long, and the floating-point pipeline ten stages. The first four stages of both pipelines are identical and are implemented by the I-Box.
I-box The I-box is the control unit; it fetches, decodes, and issues instructions and controls the pipeline.Digital Equipment Corporation 1996, p. 2-3–2-4 During stage one, two instructions are fetched from the I-cache. Branch prediction is performed by logic in the I-box during stage two. Either static prediction or dynamic prediction is used. Static prediction examined the sign bit of the displacement field of a branch instruction, predicted the branch as taken if the sign bit indicated a backwards branch (if sign bit contained 1). Dynamic prediction examined an entry in the 2,048-entry by 1-bit branch history table. If an entry contained 1, the branch was predicted as taken.Digital Equipment Corporation 1996, p. 2-5 If dynamic prediction was utilized, the branch prediction is approximately 80% accurate for most programs. The branch misprediction penalty is four cycles.Dobberpuhl 1992, p. 37
These instructions are decoded during stage three. The I-box then checks if the resources required by the two instructions are available during stage four. If so, the instructions are issued, providing they can be paired. Which instructions could be paired was determined by the number of read and write ports in the integer register file. The 21064 could issue: an integer operate with a floating-point operate, any load/store instruction with any operate instruction, an integer operate with an integer branch, or a floating-point operate with a floating-point branch. Two combinations were not permitted: an integer operate and a floating-point store, and a floating-point operate and an integer store. If one of the two instructions cannot be issued together, the first four stages are stalled until the remaining instruction is issued. The first four stages are also stalled in the event that no instruction can be issued due to resource unavailability, dependencies, or similar conditions.
The I-box contains two translation lookaside buffers (TLBs) for translating virtual addresses to physical addresses. These TLBs are referred to as instruction translation buffers (ITBs). The ITBs cache recently used page table entries for the instruction stream. An eight-entry ITB is used for 8 KB pages and a four-entry ITB for 4 MB pages. Both ITBs are fully associative and use a not-last used replacement algorithm.Digital Equipment Corporation 1996, p. 2-6
Execution Execution begins during stage five for all instructions. The register files are read during stage four. The pipelines beginning at stage five cannot be stalled.
Integer unit The integer unit is responsible for executing integer instructions. It consists of the integer register file (IRF) and the E-box. The IRF contains thirty-two 64-bit registers and has four read ports and two write ports that are equally divided between the integer unit and the branch unit.Dobberpuhl 1992, pp. 35–36 The E-box contains an adder, a logic unit, barrel shifter, and multiplier. Except for multiply, shift, and byte manipulation instructions, most integer instructions are completed by the end of stage five and thus have a latency of one cycle. The barrel shifter is pipelined, but shift and byte manipulation instructions are not completed by the end of stage six, and thus have a latency of two cycles. The multiplier was not pipelined in order to save die area;McLellan 1993, p. 42 thus multiply instructions have a variable latency of 19 to 23 cycles depending on the operands. In stage seven, integer instructions write their results to the IRF.
Address unit The address unit, also known as the "A-box", executed load and store instructions. To enable the address unit and integer unit to operate in parallel, the address unit has its own displacement adder, which it uses to calculate virtual addresses, instead of using the adder in the integer unit.McLellan 1993, p. 43 A 32-entry fully associative translation lookaside buffer (TLB) is used to translate virtual addresses into physical addresses. This TLB is referred to as the data translation buffer (DTB). The 21064 implemented a 43-bit virtual address and a 34-bit physical address, and is therefore capable of addressing 8 TB of virtual memory and 16 GB of physical memory.
Store instructions result in data buffered in a 4-entry by 32-byte write buffer. The write buffer improved performance by reducing the number of writes on the system bus by merging data from adjacent stores and by temporarily delaying stores, enabling loads to be serviced quicker as the system bus is not utilized as often.
Floating-point unit The floating-point unit consists of the floating-point register file (FRF) and the F-box.Dobberpuhl 1992, p. 36 The FRF contains thirty-two 64-bit registers and has three read ports and two write ports. The F-box contained a floating-point pipeline and a non-pipelined divide unit which retired one bit per cycle.
The floating-point register file is read and the data formatted into fraction, exponent, and sign in stage four. If executing add instructions, the adder calculates the exponent difference, and a predictive leading one or zero detector using input operands for normalizing the result is initiated. If executing multiply instructions, a 3 X multiplicand is generated.
In stages five and six, alignment or a normalization shift and sticky-bit calculations are performed for adds and subtracts. Multiply instructions are multiplied in a pipelined, two-way interleaved array which uses a radix-8 Booth algorithm.Dobberpuhl 1992, p. 38 In stage eight, final addition is performed in parallel with rounding. Floating-point instructions write their results to the FRF in stage ten.
Instructions executed in the pipeline have a six-cycle latency. Single-precision (32-bit) and double-precision (64-bit) divides, which are executed in the non-pipelined divide unit, have a latency of 31 and 61 cycles, respectively.Gwennap 1994
Caches The 21064 has two on-die primary caches: an 8 KB data cache (known as the D-cache) using a write-through write policy and an 8 KB instruction cache (known as the I-cache). Both caches are direct-mapped for single-cycle access and have 32-byte line size. The caches are built with six-transistor static random access memory (SRAM) cells that have an area of 98 μm2. The caches are 1,024 cells wide by 66 cells tall, with the top two rows used for redundancy.
An optional external secondary cache, known as the B-cache, with capacities of 128 KB to 16 MB was supported. The cache operated at one-third to one-sixteenth of the internal clock frequency, or 12.5 to 66.67 MHz at 200 MHz.McLellan 1993, p. 44 The B-cache is direct-mapped and has a 128-byte line size by default that could be configured to use larger quantities. The B-cache is accessed via the system bus.
External interface The external interface is a 128-bit data bus that operated at half to one-eighth the internal clock rate, or 25 to 100 MHz at 200 MHz. The width of the bus was configurable, systems using the 21064 could have a 64-bit external interface. The external interface also consisted of a 34-bit address bus.
Fabrication