Around the time that the Pentium 4 processor was introduced, Intel's Xeon line diverged from its line of desktop processors, which at the time was using the Pentium branding.

The divergence was implemented by using different sockets; since then, the sockets for Xeon chips have tended to remain constant across several generations of implementation.

The chipsets contain a 'memory controller hub' and an 'I/O controller hub', which tend to be called 'north bridge' and 'south bridge' respectively. The memory controller hub connects to the processors, memory, high-speed I/O such as PCI Express, and to the I/O controller hub by a proprietary link. The I/O controller hub, on the other hand, connects to lower-speed I/O, such as SATA, PCI, USB, and Ethernet.

P6-based Xeon chipsets

Dual-processor P6-based Xeon chipsets

Intel's initial preferred chipset for Pentium III Xeon was the 840.

Product name Codename Processor FSB supported Memory type supported High-speed interfaces provided Preferred IOCH 440GX AGPset Marlinespike 100 One 72-bit-wide channel of SDRAM, with ECC; up to four DIMMs PIIX4E 840 Carmel 100 or 133 Two channels RDRAM, two RIMMs per channel

Four-processor P6-based Xeon chipsets

The Pentium III Xeon bus protocol allowed four processors on the same bus, so the 440GX AGPset could be used in four-CPU systems; the limit of 2 GB of main memory remained. These support Slot 2.

There was also the 450NX PCIset, which consisted of several chips: a single 82451NX Memory and IO Bridge Controller roughly analogous to the North Bridge, up to two 82454NX PCI Expander Bridges which converted the protocol used by 451NX to two 32-bit PCI33 or one 64-bit PCI33 bus, along with up to two memory cards each equipped with one 82452NX RAS/CAS Generator chip and two 82453NX Data Path Multiplexer chips. It supported PIIX3 and PIIX4E south bridges, and EDO DRAM.

Eight-processor P6-based Xeon chipset

In August 1999, Intel began shipping the Profusion PCIset. The chipset was based on technology developed by the Corollary company, which Intel acquired. It supported up to 8 Pentium III Xeon processors on two busses and maintained cache coherency between them. Profusion supported up to 32 GB of memory. It saw some limited competition from the NEC Aqua II chipset. Another minor player in the eight-way space was Axil Computer's NX801, which was used in an 8-way (two buses) Pentium Pro design, commercialized by Data General as their AV-8600 computer.

NetBurst-based Xeon chipsets

Dual-processor NetBurst-based Xeon chipsets

E7500 corresponded to the first Northwood-based Pentium4 Xeons, E7501 is essentially identical but supports faster FSB and memory. The E7320, E7520 and E7525 chipsets correspond to Prescott-based Pentium4 Xeons, and differ mainly in their PCI Express support. These support Socket 604. The Intel 875P chipset was used in some two-socket motherboards for Xeons.

Product name Codename Processor FSB supported Memory type supported High-speed interfaces provided Preferred IOCH 860 Colusa 400 MT/s Two channels of ECC RDRAM at 800 or 600 MT/s, up to 3.2 GB/s AGP 4× port and three hub interfaces for two 533 MB/s PCI buses and a 266 MB/s bus to ICH2 ICH2 E7205 Granite Bay 400 or 533 MT/s Two channels of DDR at 100 MHz or 133 MHz AGP 8× port, single 32-bit 33 MHz PCI bus, 266 MHz 8-bit hub interface for ICH4 ICH4 E7210 Canterwood-ES 400 MT/s, 533 MT/s or 800 MT/s Two channels of unbuffered ECC and non-ECC DDR DIMMs (registered ECC is not supported) at 133 MHz, 166 MHz or 200 MHz (DDR-266/333/400) 66 MHz CSA interface for Gigabit LAN. MCH is connected to ICH via 66 MHz 8-bit (266 MT/s) Hub Interface v1.5. A 6300ESB ICH provides up to four 32-bit and/or 64-bit PCI-X at 33 or 66 MHz. Intel E7210 is server variant of 875P (Socket 478) without AGP, it can be used in dual Socket 604 configurations. 6300ESB E7320 Lindenhurst VS 800 MT/s Two channels of registered DDR-333 or DDR2-400 SDRAM One ×8 PCI Express interface with max. theoretical bandwidth of 4GB/s, which may be configured as two ×4 PCIe interfaces. A 6700PXH provides PCI-X 32-bit and/or 64-bit interfaces at 33 MHz, 66 MHz, 100 MHz, and 133 MHz. 6300ESB, or 82801ER (ICH5R) E7500Plumas 400 MT/s Two channels of ECC DDR SDRAM at 100 MHz (3.2 GB/s peak)Three ECC 1 GB/s (66 MHz ×8, 16-bit) 'Hub Interface' channels, which connect to 82870P2 chips to provide two 64-bit 66 MHz PCI or PCI-X buses each, plus one ECC 533 MB/s (66 MHz ×4) connector for ICH3-SICH3-S E7501Plumas 533 533 MT/s Two channels of ECC DDR SDRAM at 133 MHz (4.2 GB/s peak) E7505 Placer 533 MT/s Two channels of ECC DDR SDRAM at 133 MHz (4.2 GB/s peak) AGP 8× port, three ECC 1 GB/s (66 MHz ×8, 16-bit) 'Hub Interface' channels, which connect to 82870P2 chips to provide two 64-bit 66 MHz PCI or PCI-X buses each, plus one ECC 533 MB/s (66 MHz ×4) connector for ICH4 ICH4 E7520 Lindenhurst800 MT/sTwo channels of registered DDR-333 or DDR2-400 SDRAM Three ×8 PCI Express interfaces each with max. theoretical bandwidth of 4GB/s, which may be configured as two ×4 PCIe interfaces. A 6700PXH provides PCI-X 32-bit and/or 64-bit interfaces at 33 MHz, 66 MHz, 100 MHz, and 133 MHz.6300ESB, or 82801ER (ICH5R) E7525 Tumwater One ×16 and one ×8 PCI Express interface. A 6700PXH can be attached.

Note that the 82870P2 chips of E7500, E7501 and E7505 were initially designed for the Intel 870 chipset for Itanium 2, and that the summary page of the E7320 datasheet incorrectly claims three PCI Express interfaces.

Quad-processor NetBurst-based Xeon chipsets As Intel didn't have a 4P-capable chipset for NetBurst-based Xeons until 2005, for three years ServerWorks GC-HE served as the de facto standard MP chipset, even being used in Intel's own motherboards (SPSH4 and SRSH4). Product name Codename Processor FSB supported Memory type supported High-speed interfaces provided Preferred IOCH E8500Intel® E8500 Chipset North Bridge (NB) DatasheetTwin Castle 667 MT/s dual busDDR-266, DDR-333 or DDR2-400three ×8 and one ×4 PCI Express interface82801EB (ICH5), or 82801ER (ICH5R) E8501Intel® E8501 Chipset North Bridge (NB) Datasheet 667 and 800 MT/s dual bus

Core-based Xeon chipsets

Single-processor Core-based Xeon chipsets

3000 and 3010 are an update on the E7230 chipset, codenamed Mukilteo, which has specifications very similar to the 3000 chipset. E7230 was preceded by E7221, which was Intel's first strictly single-socket server chipset. Product name Codename Processor FSB supported Memory type supported High-speed interfaces provided Preferred IOCH 3000 Mukilteo-2Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet: https://www.mouser.com/pdfdocs/3010datasheet.pdfShort description of the Intel® 3000 and 3010 Chipsets: https://datasheets.globalspec.com/ps/4188/Intel/D9CD201F-BD9A-4B47-A6AF-D2100F8046F4533 or 800 or 1066 MT/sTwo channels of ECC DDR2-533 or DDR2-667 PCI Express ×8 port, single 32-bit 33 MHz PCI bus, DMI for ICH7ICH7 3010 Mukilteo-2P PCI Express 1 ×16 or 2 ×8 ports, single 32-bit 33 MHz PCI bus, DMI for ICH7 3200 Bigby-V800 or 1066 or 1333 MT/sTwo channels of ECC DDR2-667 or DDR2-800 PCI Express ×8 port, single 32-bit 33 MHz PCI bus, DMI for ICH9ICH9 3210 Bigby-P PCI Express 1 ×16 or 2 ×8 ports, single 32-bit 33 MHz PCI bus, DMI for ICH9

Dual-processor Core-based Xeon chipsets

These chipsets use a 'dual independent bus' design, in which each socket has its own connection to the chipset. These use the LGA 771 socket. The datasheets omit the 667 MT/s FSB support, so 5400 may support it too.

Product name Codename FSB speed(MT/s) Snoop filter Memory support High-speed interfaces provided Preferred IOCH 5000PBlackford667, 1066, 1333 Four channels of FB-DIMM at 533 or 667 MHz, up to 64 GB Six PCIe ×4 ports, of which two are normally used for communication with IOCH, and a seventh ×4 port only for IOCH.631xESB or 632xESB 5000ZTwo channels of FB-DIMM at 533 or 667 MHz, up to 16 GB Four PCIe ×4 ports, of which two are normally used for communication with IOCH, and a fifth ×4 port only for IOCH. 5000V Two PCIe ×4 ports which are normally used for communication with IOCH, and a third ×4 port only for IOCH. 5000X Greencreek A snoop filter comprising about 1 MB of SRAM for coverage of 16 MB of cache. Four channels of FB-DIMM at 533 or 667 MHz, up to 64 GB Six PCIe ×4 ports, of which two are normally used for communication with IOCH and the other four are combined into a ×16 port, and a seventh ×4 port only for IOCH. 5100 San Clemente Two channels of registered ECC DDR2 533 or 667 MT/s, up to 48 GB 6 PCIe ×4 ports, plus one ×4 port reserved for IOCH ICH9R 5400 Seaburg 1066, 1333, 1600 A more advanced snoop filter comprising about 1.6 MB of SRAM for coverage of 24 MB of cache. Four channels of FB-DIMM at 533, 667 or 800 MHz, up to 128 GB 9 PCIe ×4 ports, plus one ×4 port reserved for IOCH 631xESB or 632xESB

Four-processor Core-based Xeon chipsets

This chipset uses four independent buses, and is used by the Tigerton and Dunnington processors.

Launch name Codename FSB speed Snoop filter Memory support Fast I/O IOCH 7300 Clarksboro 1066 MT/s A very sophisticated snoop filter, comprising 4.5 MB of SRAM for coverage of 64 MB of cache. Four channels of FB-DIMM at 533 or 667 MHz, up to 256 GB 7 PCIe ×4 ports, of which two are usually used to connect to the IOCH, plus an 8th ×4 port only for IOCH 631x or 632x

Nehalem-based Xeon chipsets

Single-processor Nehalem-based Xeon chipsets

The 3450 chipset is also compatible with an Intel Core i5 or Intel Core i3 processor.

Product name Codename DMI Fast I/O Other features 3400 Ibex Peak 1.0, 100 MT/s PCI Express 6 ×1 ports, single 32-bit 33 MHz PCI bus, DMI for processor 8× USB 2.0, 4× SATA, Integrated LAN 3420 Ibex Peak 1.0, 100 MT/s PCI Express 8 ×1 ports, single 32-bit 33 MHz PCI bus, DMI for processor 12× USB 2.0, 6× SATA, Integrated LAN 3450 Ibex Peak 1.0, 100 MT/s PCI Express 8 ×1 ports, single 32-bit 33 MHz PCI bus, DMI for processor 14× USB 2.0, 6× SATA, Integrated LAN

Dual-processor Nehalem-based Xeon chipsets

The Nehalem-based Xeons for dual-socket systems, initially launched as the Xeon 55xx series, feature a very different system structure: the memory controllers are on the CPU, and the CPUs can communicate with one another as peers without going via the chipset. This means that the 5500 and 5520 (initial codename Tylersburg-EP) chipsets are essentially QPI to PCI Express interfaces; the 5520 is more intended for graphical workstations and the 5500 for servers that do not need vast amounts of PCI Express connectivity

Launch name Codename QPI ports QPI speed Fast I/O IOCH Other features 5500 Tylersburg-24S,Tylersburg-24D 1,2 4.8, 5.86 or 6.4 GT/s 1 ×16 PCIe Gen 2, 2 ×4 PCIe Gen 1 to talk to southbridge ICH10 (ICH9 also possible) Integrated Management Engine with its own 100 Mbit/s Ethernet 5520 Tylersburg-36S,Tylersburg-36D 1,2 4.8, 5.86 or 6.4 GT/s 2 ×16 PCIe Gen 2, 1 ×4 PCIe Gen 1 to talk to southbridge ICH10 (ICH9 also possible) Integrated Management Engine with its own 100 Mbit/s Ethernet

As well as the 5530

Four-processor Nehalem-based Xeon chipsets Launch name Codename QPI ports QPI speed Fast I/O IOCH Other features 7500 Boxboro 2 6.4 GT/s 2 ×16 PCIe Gen 2, 1 ×4 PCIe Gen 1 to talk to southbridge ICH10 (ICH9 also possible) Integrated Management Engine with its own 100 Mbit Ethernet

Sandy Bridge-based Xeon chipsets

Single-processor Sandy Bridge-based Xeon chipsets The Intel C200 series chipsets that support the Intel Xeon E3-1200 CPU family.Intel® 6 Series Chipset and Intel® C200 Series ChipsetSemiAccurate: Intel's C200 E3-series Xeon chipsets detailed by Lars-Göran Nilsson