A phase-locked loop (PLL) is a control system that generates an output signal whose phase is fixed relative to the phase of an input signal. Keeping the input and output phase in lockstep also implies a constant relationship between input and output frequencies. By incorporating a frequency divider, a PLL can generate a stable frequency that is a multiple of the input frequency.
These properties are used for clock synchronization, demodulation, frequency synthesis, clock multipliers, and signal recovery from a noisy communication channel. Since 1969, a single integrated circuit can provide a complete PLL building block, and nowadays has output frequencies from a fraction of a hertz up to many gigahertz. Thus, PLLs are widely employed in radio, telecommunications, computers (e.g. to distribute precisely timed clock signals in microprocessors), grid-tie inverters (electronic power converters used to integrate DC renewable resources and storage elements such as photovoltaics and batteries with the power grid), and other electronic applications.
Simple example
A simple analog PLL is an electronic circuit consisting of a variable frequency oscillator and a phase detector in a feedback loop (Figure 1). The oscillator generates a periodic signal with frequency proportional to an applied voltage, hence the term voltage-controlled oscillator (VCO). The phase detector compares the phase of the VCO's output signal with the phase of periodic input reference signal and outputs a voltage (stabilized by the filter) to adjust the oscillator's frequency to match the phase of to the phase of .
Clock analogy Phase can be proportional to time, so a phase difference can correspond to a time difference.
Left alone, different clocks will mark time at slightly different rates. A mechanical clock, for example, might be fast or slow by a few seconds per hour compared to a reference atomic clock (such as the NIST-F2). That time difference becomes substantial over time. Instead, the owner can synchronize their mechanical clock (with varying degrees of accuracy) by phase-locking it to a reference clock. An inefficient synchronization method involves the owner resetting their clock to that more accurate clock's time every week. But, left alone, their clock will still continue to diverge from the reference clock at the same few seconds per hour rate.
A more efficient synchronization method (analogous to the simple PLL in Figure 1) utilizes the fast-slow timing adjust control (analogous to how the VCO's frequency can be adjusted) available on some clocks. Analogously to the phase comparator, the owner could notice their clock's misalignment and turn its timing adjustment a small proportional amount to make their clock's frequency a little slower (if their clock was fast) or faster (if their clock was slow). If they don't overcompensate, then their clock will be more accurate than before. Over a series of such weekly adjustments, their clock's notion of a second would agree close enough with the reference clock, so they could be said to be locked both in frequency and phase.
An early electromechanical version of a phase-locked loop was used in 1921 in the Shortt-Synchronome clock.
History Spontaneous synchronization of weakly coupled pendulum clocks was noted by the Dutch physicist Christiaan Huygens as early as 1673.Christiaan Huygens, Horologium Oscillatorium … (Paris, France: F. Muguet, 1673), pages 18–19. From page 18: " … illudque accidit memoratu dignum, … brevi tempore reduceret." (… and it is worth mentioning, since with two clocks constructed in this form and which we suspend in like manner, truly the cross beam is assigned two fulcrums [i.e., two pendulum clocks were suspended from the same wooden beam]; the motions of the pendulums thus share the opposite swings between the two [clocks], since the two clocks at no time move even a small distance, and the sound of both can be heard clearly together always: for if the innermost part [of one of the clocks] is disturbed with a little help, it will have been restored in a short time by the clocks themselves.) English translation provided by Ian Bruce's translation of Horologium Oscillatorium … , pages 16–17. Around the turn of the 19th century, Lord Rayleigh observed synchronization of weakly coupled organ pipes and tuning forks.See: Lord Rayleigh, The Theory of Sound (London, England: Macmillan, 1896), vol. 2. The synchronization of organ pipes in opposed phase is mentioned in §322c, pages 221–222. Lord Rayleigh (1907) "Acoustical notes — VII", Philosophical Magazine, 6th series, 13 : 316–333. See "Tuning-forks with slight mutual influence", pages 322–323. In 1919, W. H. Eccles and J. H. Vincent found that two electronic oscillators that had been tuned to oscillate at slightly different frequencies but that were coupled to a resonant circuit would soon oscillate at the same frequency.See: Vincent (1919) "On some experiments in which two neighbouring maintained oscillatory circuits affect a resonating circuit", Proceedings of the Physical Society of London, 32, pt. 2, 84–91. W. H. Eccles and J. H. Vincent, British Patent Specifications, 163 : 462 (17 Feb. 1920). Automatic synchronization of electronic oscillators was described in 1923 by Edward Victor Appleton.E. V. Appleton (1923) "The automatic synchronization of triode oscillators", Proceedings of the Cambridge Philosophical Society, 21 (Part III): 231–248. Available on-line at: Internet Archive.
In 1923, Harry Nyquist patented a PLL with a motor-generator as the oscillator.
In 1925, David Robertson, the first professor of electrical engineering at the University of Bristol, introduced phase locking in his clock design to control the striking of the bell Great George in the new Wills Memorial Building. Robertson's clock incorporated an electromechanical device that could vary the rate of oscillation of the pendulum, and derived correction signals from a circuit that compared the pendulum phase with that of an incoming telegraph pulse from Greenwich Observatory every morning at 10:00 GMT. Including equivalents of every element of a modern electronic PLL, Robertson's system was notably ahead of its time in that its phase detector was a relay logic implementation of the transistor circuits for phase/frequency detectors not seen until the 1970s.
Robertson's work predated research towards what was later named the phase-lock loop in 1932, when British researchers developed an alternative to Edwin Armstrong's superheterodyne receiver, the Homodyne or direct-conversion receiver. In the homodyne or synchrodyne system, a local oscillator was tuned to the desired input frequency and multiplied with the input signal. The resulting output signal included the original modulation information. The intent was to develop an alternative receiver circuit that required fewer tuned circuits than the superheterodyne receiver. Since the local oscillator would rapidly drift in frequency, an automatic correction signal was applied to the oscillator, maintaining it in the same phase and frequency of the desired signal. The technique was described in 1932, in a paper by Henri de Bellescize, in the French journal L'Onde Électrique.Henri de Bellescize, "La réception synchrone", L'Onde Électrique (later: Revue de l'Electricité et de l'Electronique), vol. 11, pages 230–240 (June 1932).See also: French patent no. 635,451 (filed: 6 October 1931; issued: 29 September 1932); and U.S. patent "Synchronizing system", no. 1,990,428 (filed: 29 September 1932; issued: 5 February 1935).Notes for a University of Guelph course describing the PLL and early history, including an IC PLL tutorial
In analog television receivers since at least the late 1930s, phase-locked-loop horizontal and vertical sweep circuits are locked to synchronization pulses in the broadcast signal.
In 1969, Signetics introduced a line of low-cost monolithic integrated circuits like the NE565 using bipolar transistors, which were complete phase-locked loop systems on a chip, and applications for the technique multiplied. A few years later, RCA introduced the CD4046 Micropower Phase-Locked Loop using CMOS, which also became a popular integrated circuit building block.
Structure and function Phase-locked loop mechanisms may be implemented as either analog or digital circuits. Both implementations use the same basic structure.
Analog PLL circuits include four basic elements: Phase detector Low-pass filter Voltage-controlled oscillator Feedback path, which may include a frequency divider
Variations There are several variations of PLLs. Some terms that are used are "analog phase-locked loop" (APLL), also referred to as a linear phase-locked loop" (LPLL), "digital phase-locked loop" (DPLL), "all digital phase-locked loop" (ADPLL), and "software phase-locked loop" (SPLL).
Analog or linear PLL (APLL) Phase detector is an analog multiplier. Loop filter is active or passive. Uses a voltage-controlled oscillator (VCO). APLL is said to be a type II if its loop filter has a transfer function with exactly one pole at the origin (see also Egan's conjecture on the pull-in range of type II APLL). Digital PLL (DPLL) An analog PLL with a digital phase detector (such as XOR, edge-triggered JK flip flop, phase frequency detector). May have a digital divider in the loop. All digital PLL (ADPLL) Phase detector, filter and oscillator are digital. Uses a numerically controlled oscillator (NCO). Neuronal PLL (NPLL) Phase detector is implemented by neuronal non-linearity, and the oscillator by rate-controlled oscillating neurons.Ahissar, E. Neuronal phase-locked loops. U.S. Patent No. 6,581,046 (2003). Software PLL (SPLL) Functional blocks are implemented by software rather than specialized hardware. Charge-pump PLL (CP-PLL) CP-PLL is a modification of phase-locked loops with a phase-frequency detector and square waveform signals. See also Gardner's conjecture on CP-PLL.
Performance parameters
Type and order. Frequency ranges: hold-in range (tracking range), pull-in range (capture range, acquisition range), lock-in range. See also Gardner's problem on the lock-in range, Egan's conjecture on the pull-in range of type II APLL, Viterbi's problem on the PLL ranges coincidence. Loop bandwidth: Defining the speed of the control loop. Transient response: Like overshoot and settling time to a certain accuracy (like 50 ppm). Steady-state errors: Like remaining phase or timing error. Output spectrum purity: Like sidebands generated from a certain VCO tuning voltage ripple. Phase-noise: Defined by noise energy in a certain frequency band (like 10 kHz offset from carrier). Highly dependent on VCO phase-noise, PLL bandwidth, etc. General parameters: Such as power consumption, supply voltage range, output amplitude, etc.
Applications Phase-locked loops are widely used for synchronization purposes; in space communications for coherent demodulation and threshold extension, bit synchronization, and symbol synchronization. Phase-locked loops can also be used to demodulate frequency-modulated signals. In radio transmitters, a PLL is used to synthesize new frequencies which are a multiple of a reference frequency, with the same stability as the reference frequency.
Other applications include: Demodulation of frequency modulation (FM): If PLL is locked to an FM signal, the VCO tracks the instantaneous frequency of the input signal. The filtered error voltage, which controls the VCO and maintains lock with the input signal, is the demodulated FM output. The VCO transfer characteristics determine the linearity of the demodulated output. Since the VCO used in an integrated-circuit PLL is highly linear, it is possible to realize highly linear FM demodulators. Demodulation of frequency-shift keying (FSK): In digital data communication and computer peripherals, binary data is transmitted by means of a carrier frequency which is shifted between two preset frequencies.