The Platform Controller Hub (PCH) is a family of Intel's single-chip chipsets, first introduced in 2009. It is the successor to the Intel Hub Architecture, which used two chipsa northbridge and southbridge, and first appeared in the Intel 5 Series.

The PCH controls certain data paths and support functions used in conjunction with Intel CPUs. These include clocking (the system clock), Flexible Display Interface (FDI) and Direct Media Interface (DMI), although FDI is used only when the chipset is required to support a processor with integrated graphics. As such, I⁠/⁠O functions are reassigned between this new central hub and the CPU compared to the previous architecture: some northbridge functions, the memory controller and PCIe lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge. AMD has its equivalent for the PCH, known simply as a chipset since the release of the Zen architecture in 2017. AMD no longer uses its equivalent for the PCH, the Fusion controller hub (FCH).

Overview

The PCH architecture supersedes Intel's previous Hub Architecture, with its design addressing the eventual problematic performance bottleneck between the processor and the motherboard. Under the Hub Architecture, a motherboard would have a two-piece chipset consisting of a northbridge chip and a southbridge chip. Over time, the speed of CPUs kept increasing but the bandwidth of the front-side bus (FSB) (connection between the CPU and the motherboard) did not, resulting in a performance bottleneck.

As a solution to the bottleneck, several functions belonging to the traditional northbridge and southbridge chipsets were rearranged. The northbridge and its functions are now eliminated completely: The memory controller, PCI Express lanes for expansion cards and other northbridge functions are now incorporated into the CPU die as a system agent (Intel) or packaged in the processor on an I⁠/⁠O die (AMD Zen 2).

The PCH then incorporates a few of the remaining northbridge functions (e.g. clocking) in addition to all of the southbridge's functions, replacing it. The system clock was previously a connection to a dedicated chip but is now incorporated into the PCH. Two different connections exist between the PCH and the CPU: Flexible Display Interface (FDI) and Direct Media Interface (DMI). The FDI is used only when the chipset requires supporting a processor with integrated graphics. The Intel Management Engine was also moved to the PCH starting with the Nehalem processors and 5-Series chipsets. The chipset also contains the Nonvolatile BIOS memory.

With the northbridge functions integrated to the CPU, much of the bandwidth needed for chipsets is now relieved.

This style began in Nehalem and will remain for the foreseeable future, through Cannon Lake.

Phase-out Beginning with ultra-low-power Haswells and continuing with mobile Skylake processors, Intel incorporated the southbridge IO controllers into the CPU package, eliminating the PCH for a system in package (SiP) design with two dies; the larger die being the CPU die, the smaller die being the PCH die. Rather than DMI, these SOPs directly expose PCIe lanes, as well as SATA, USB, and HDA lines from integrated controllers, and SPI/I²C/UART/GPIO lines for sensors. Like PCH-compatible CPUs, they continue to expose DisplayPort, RAM, and SMBus lines. However, a fully integrated voltage regulator will be absent until Cannon Lake.

AMD equivalent

The AMD equivalent to PCH is known as the FCH. It is linked to the CPU through the UMI bus and provides southbridge functions.

AMD has used a system-on-chip (SoC) design on desktop and server processors since 2015 with the Excavator Carrizo core. What is known as the "chipset" is instead a special PCIe device that combines the functionalities of an PCIe switch (which expands the number of available PCIe lanes), a USB host, and/or a SATA host. This device connects to the CPU via a dedicated PCIe link. Non-HEDT desktop processors since Zen 2 (2019) instead use a MCM design with separate CPU and I/O dies (system in package) to improve yields.

AMD server and laptop CPUs adopt a self contained system on chip (SoC) design instead which doesn't require a chipset.

Ibex Peak

The Intel 5 Series chipsets were the first to introduce a PCH. This first PCH is codenamed Ibex Peak.

This has the following variations: BD3400 (PCH 3400) Server BD3420 (PCH 3420) Server BD3450 (PCH 3450) Server BD82P55 (PCH P55) Desktop Base BD82H55 (PCH H55) Desktop Home BD82H57 (PCH H57) Desktop Home BD82Q57 (PCH Q57) Desktop Office BD82PM55 (PCH PM55) Mobile Base BD82HM55 (PCH HM55) Mobile Home BD82HM57 (PCH HM57) Mobile Home BD82QM57 (PCH QM57) Mobile Office BD82QS57 (PCH QS57) Mobile SFF

Issues Bogus USB ports will be detected by desktop PCHs equipped with 6 USB ports (3420, H55) on the first EHCI controller. This can happen when AC power is removed after entering ACPI S4. Applying AC power back and resuming from S4 may result in non detected or even non functioning USB device (erratum 12) Bogus USB ports will be detected by mobile PCH equipped with 6 USB ports (HM55) on the first EHCI controller. This can happen when AC power and battery are removed after entering ACPI S4. Applying AC power or battery back and resuming from S4 may result in non detected or even non functioning USB device (erratum 13) Reading the HPET comparator timer immediately after a write returns the old value (erratum 14) SATA 6 Gbit/s devices may not be detected at cold boot or after ACPI S3, S4 resume (erratum 21)

Langwell Langwell is the codename of a PCH in the Moorestown MID/smartphone platform. for Atom Lincroft microprocessors.

This has the following variations: AF82MP20 (PCH MP20) AF82MP30 (PCH MP30)

Tiger Point

Tiger Point is the codename of a PCH in the Pine Trail netbook platform chipset for Atom Pineview microprocessors.

This has the following variations: CG82NM10 (PCH NM10)

Topcliff Topcliff is the codename of a PCH in the Queens Bay embedded platform chipset for Atom Tunnel Creek microprocessors.

It connects to the processor via PCIe (vs. DMI as other PCHs do).

This has the following variations: CS82TPCF (PCH EG20T)

Cougar Point

Cougar Point is the codename of a PCH in Intel 6 Series chipsets for mobile, desktop, workstation, and server platforms. It is most closely associated with Sandy Bridge processors.

This has the following variations: BD82C202 (PCH C202) Server BD82C204 (PCH C204) Server BD82C206 (PCH C206) Workstation and Server BD82P67 (PCH P67) Desktop Base BD82H67 (PCH H67) Desktop Home BD82H61 (PCH H61) Desktop Home BD82Z68 (PCH Z68) Combined desktop base and home BD82B65 (PCH B65) Desktop Office BD82Q67 (PCH Q67) Desktop Office BD82Q65 (PCH Q65) Desktop Office BD82HM65 (PCH HM65) Mobile Home BD82HM67 (PCH HM67) Mobile Home BD82QM67 (PCH QM67) Mobile Office BD82QS67 (PCH QS67) Mobile SFF BD82UM67 (PCH UM67) Ultra Mobile

Issues

In the first month after Cougar Point's release, January 2011, Intel posted a press release stating a design error had been discovered. Specifically, a transistor in the 3 Gbit/s PLL clocking tree was receiving too high voltage. The projected result was a 5–15% failure rate within three years of 3 Gbit/s SATA ports, commonly used for storage devices such as hard drives and optical drives. The bug was present in revision B2 of the chipsets, and was fixed with B3. Z68 did not have this bug, since the B2 revision for it was never released. 6 Gbit/s ports were not affected. This bug was especially a problem with the H61 chipset, which only had 3 Gbit/s SATA ports. Through OEMs, Intel plans to repair or replace all affected products at a cost of $700 million.

Nearly all produced motherboards using Cougar Point chipsets were designed to handle Sandy Bridge, and later Ivy Bridge, processors. ASRock produced one motherboard for LGA 1156 processors, based on P67 chipset, the P67 Transformer. It exclusively supports Lynnfield Core i5/i7 and Xeon processors, using LGA 1156 socket. After revision B2 of Cougar Point chipsets was recalled, ASRock decided not to update the P67 Transformer motherboard, and was discontinued. Some small Chinese manufacturers are producing LGA 1156 motherboards with H61 chipset.

Whitney Point Whitney Point is the codename of a PCH in the Oak Trail tablet platform for Atom Lincroft microprocessors.

This has the following variations: 82SM35 (PCH SM35)

Panther Point

Panther Point is the codename of a PCH in Intel 7 Series chipsets for mobile and desktop. It is most closely associated with Ivy Bridge processors. These chipsets (except PCH HM75) have integrated USB 3.0.

This has the following variations: BD82C216 (PCH C216) Workstation/Server BD82H77 (PCH H77) Desktop Home BD82Z77 (PCH Z77) Combined desktop base and home BD82Z75 (PCH Z75) Combined desktop base and home BD82B75 (PCH B75) Desktop Office BD82Q77 (PCH Q77) Desktop Office BD82Q75 (PCH Q75) Desktop Office BD82HM77 (PCH HM77) Mobile Home BD82HM76 (PCH HM76) Mobile Home BD82HM75 (PCH HM75) Mobile Home BD82HM70 (PCH HM70) Mobile Home BD82QM77 (PCH QM77) Mobile Office BD82QS77 (PCH QS77) Mobile Office BD82UM77 (PCH UM77) Ultra Mobile

Cave Creek Cave Creek is the codename of the PCH most closely associated with Crystal Forest platforms and Gladden or Sandy Bridge-EP/EN processors. DH8900 (PCH 8900) Communications DH8903 (PCH 8903) Communications DH8910 (PCH 8910) Communications DH8920 (PCH 8920) Communications

Patsburg Patsburg is the codename of a PCH in Intel 7 Series chipsets for server and workstation using the LGA 2011 socket. It was initially launched in 2011 as part of Intel X79 for the desktop enthusiast Sandy Bridge-E processors in Waimea Bay platforms. Patsburg was then used for the Sandy Bridge-EP server platform (the platform was codenamed Romley and the CPUs codenamed Jaketown, and finally branded as Xeon E5-2600 series) launched in early 2012.

Launched in the fall of 2013, the Ivy Bridge-E/EP processors (the latter branded as Xeon E5-2600 v2 series) also work with Patsburg, typically with a BIOS update.

Patsburg has the following variations: BD82C602 (PCH C602) Server BD82C602J (PCH C602J) Server BD82C604 (PCH C604) Server BD82C606 (PCH C606) Workstation and Server BD82C608 (PCH C608) Workstation and Server BD82X79 (PCH X79) Workstation

Coleto Creek Coleto Creek is the codename of the PCH most closely associated with Highland Forest platforms and Ivy Bridge-EP processors. DH8925 (PCH 8925) Communications DH8926 (PCH 8926) Communications DH8950 (PCH 8950) Communications DH8955 (PCH 8955) Communications

Lynx Point

Lynx Point is the codename of a PCH in Intel 8 Series chipsets, most closely associated with Haswell processors with LGA 1150 socket. The Lynx Point chipset connects to the processor primarily over the Direct Media Interface (DMI) interface.

The following variants are available: DH82C222 (PCH C222) Workstation/Server DH82C224 (PCH C224) Workstation/Server DH82C226 (PCH C226) Workstation/Server DH82H81 (PCH H81) Desktop Home DH82H87 (PCH H87) Desktop Home DH82Z87 (PCH Z87) Combined desktop base and home DH82B85 (PCH B85) Desktop Office DH82Q87 (PCH Q87) Desktop Office DH82Q85 (PCH Q85) Desktop Office DH82HM87 (PCH HM87) Mobile Home DH82HM86 (PCH HM86) Mobile Home DH82QM87 (PCH QM87) Mobile Office

In addition the following newer variants are available, additionally known as Wildcat Point, which also support Haswell Refresh processors: DH82H97 (PCH H97) Desktop Home DH82Z97 (PCH Z97) Combined desktop base and home

Issues A design flaw causes devices connected to the Lynx Point's integrated USB 3.0 controller to be disconnected when the system wakes up from the S3 state (Suspend to RAM), forcing the USB devices to be reconnected although no data is lost. This issue is corrected in C2 stepping level of the Lynx Point chipset.

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