The 555 timer IC is an integrated circuit used in a variety of timer, delay, pulse generation, and oscillator applications. It is one of the most popular timing ICs due to its flexibility and price. Derivatives provide two (556) or four (558) timing circuits in one package. The design was first marketed in 1972 by Signetics and used bipolar junction transistors. Since then, numerous companies have made the original timers and later similar low-power CMOS timers. In 2017, it was said that over a billion 555 timers are produced annually by some estimates, and that the design was "probably the most popular integrated circuit ever made".
History
The timer IC was designed in 1971 by Hans Camenzind under contract to Signetics. In 1968, he was hired by Signetics to develop a phase-locked loop (PLL) IC. He designed an oscillator for PLLs such that the frequency did not depend on the power supply voltage or temperature. Signetics subsequently laid off half of its employees due to the 1970 recession, and development on the PLL was thus frozen. Camenzind proposed the development of a universal circuit based on the oscillator for PLLs and asked that he develop it alone, borrowing equipment from Signetics instead of having his pay cut in half. Camenzind's idea was originally rejected, since other engineers argued the product could be built from existing parts sold by the company; however, the marketing manager approved the idea.
The first design for the 555 was reviewed in the summer of 1971. After this design was tested and found to be without errors, Camenzind got the idea of using a direct resistance instead of a constant current source, finding that it worked satisfactorily. The design change decreased the required 9 external pins to 8, so the IC could be fit in an 8-pin package instead of a 14-pin package. This revised version passed a second design review, and the prototypes were completed in October 1971 as the NE555V (plastic DIP) and SE555T (metal TO-5). The 9-pin version had already been released by another company founded by an engineer who had attended the first review and had retired from Signetics; that firm withdrew its version soon after the 555 was released. The 555 timer was manufactured by 12 companies in 1972, and it became a best-selling product.
The 555 found many applications beyond timers. Camenzind noted in 1997 that "nine out of 10 of its applications were in areas and ways I had never contemplated. For months I was inundated by phone calls from engineers who had new ideas for using the device."
Name Several books report the name "555" timer IC derived from the three 5 kΩ resistors inside the chip. However, in a recorded interview with an online transistor museum curator, Hans Camenzind said "It was just arbitrarily chosen. It was Art Fury (marketing manager) who thought the circuit was gonna sell big who picked the name '555' timer IC."
Design Depending on the manufacturer, the standard 555 package incorporated the equivalent of 25 transistors, 2 diodes, and 15 resistors on a silicon chip packaged into an 8-pin dual in-line package (DIP-8). Variants available included the 556 (a DIP-14 combining two complete 555s on one chip), and 558 / 559 (both variants were a DIP-16 combining four reduced-functionality timers on one chip).
The NE555 parts were commercial temperature range, 0 °C to +70 °C, and the SE555 part number designated the military temperature range, −55 °C to +125 °C. These chips were available in both high-reliability metal can (T package) and inexpensive epoxy plastic (V package) form factors. Thus, the full part numbers were NE555V, NE555T, SE555V, and SE555T.
Low-power CMOS versions of the 555 are now available, such as the Intersil ICM7555 and Texas Instruments LMC555, TLC555, TLC551.
Internal schematic The internal block diagram and schematic of the 555 timer are highlighted with the same color across all three drawings to clarify how the chip is implemented: : Between the positive supply voltage VCC and the ground GND is a voltage divider consisting of three identical resistors (5kΩ for bipolar timers, 100kΩ or higher for CMOS) to create reference voltages for the analog comparators. CONTROL is connected between the upper two resistors, allowing an external voltage to control the reference voltages: When CONTROL is not driven, this divider creates an upper reference voltage of VCC and a lower reference voltage of VCC. When CONTROL is driven, the upper reference voltage will instead be VCONTROL and the lower reference voltage will be VCONTROL. : The comparator's negative input is connected to voltage divider's upper reference voltage, and the comparator's positive input is connected to THRESHOLD. : The comparator's positive input is connected to voltage divider's lower reference, and the comparator's negative input is connected to TRIGGER. : A set-reset latch stores the state of the timer and is controlled by the two comparators. RESET overrides the other two inputs, thus the latch (and therefore the entire timer) can be reset at any time. : The output of the latch is followed by an output stage with pushpull output drivers that can supply up to 200mA for bipolar timers, lower for CMOS timers. : Also, the output of the latch controls a transistor acting as an electronic switch that connects DISCHARGE to ground.
Pinout The pinout of the 8-pin 555 timer and 14-pin 556 dual timer are shown in the following table. Since the 556 is conceptually two 555 timers that share power pins, the pin numbers for each half are split across two columns.
555 pin# 556 556 Pin name Pin direction Pin description Ground supply: this pin is the ground reference voltage (zero volts). Trigger: when VTRIGGER falls below VCONTROL ( VCC, except when CONTROL is driven by an external signal), OUTPUT goes to the high state and a timing interval starts. As long as TRIGGER continues to be kept at a low voltage, OUTPUT will remain in the high state. Output: this pin is a push-pull (P.P.) output that is driven to either a low state (GND) or a high state (VCC minus approximately 1.7 volts for bipolar timers, or VCC for CMOS timers). Reset: a timing interval may be reset by driving this pin to GND, but the timing does not begin again until this pin rises above approximately 0.7 volts. This pin overrides , which in turn overrides THRESHOLD. If this pin is not used, it should be connected to VCC to prevent electrical noise accidentally causing a reset. Control: this pin provides access to the internal voltage divider ( VCC by default). By applying a voltage to this pin, the timing characteristics can be changed. In astable mode, this pin can be used to frequency-modulate the OUTPUT state. If this pin is not used, it should be connected to a 10 nF decoupling capacitor (between this pin and GND) to ensure electrical noise doesn't affect the internal voltage divider. Threshold: when the voltage at this pin is greater than VCONTROL ( VCC by default except when CONTROL is driven by an external signal), then the OUTPUT high state timing interval ends, causing OUTPUT to go to the low state. Discharge: This pin is an open-collector (O.C.) output for bipolar timers, or an open-drain (O.D.) output for CMOS timers. This pin can be used to discharge a capacitor when OUTPUT is low. In bistable latch and bistable inverter modes, this pin is unused, which allows it to be used as an alternate output. Positive supply: For bipolar timers, the supply voltage range is typically 4.5 to 16 volts (some are spec'ed for up to 18 volts, though most will operate as low as 3 volts). For CMOS timers, the supply voltage range is typically 2 to 15 volts (some are spec'ed for up to 18 volts, and some are spec'ed as low as 1 volt). See the supply min and max columns in the derivatives table in this article. Decoupling capacitor(s) are generally applied (between this pin and GND) as a good practice.
Modes The 555 IC has the following operating modes: Astable (free-running) mode – The 555 operates as an electronic oscillator. Applications include: As a general-purpose oscillator or clock/periodic timer, which may be used for many things including: Light emitting diode and lamp flashers, pulse generation, pulse-width modulation (PWM), logic clocks, tone generation, security alarms, pulse-position modulation, etc. Analog-to-digital conversion (ADC) from an analog value represented by a resistance or capacitance into a digital pulse length. e.g., selecting a thermistor as timing resistor allows the use of the 555 in a temperature sensor with the period of the output pulse determined by the temperature. A microprocessor can then convert the pulse period to temperature, linearize it, and even provide calibration. Monostable (one-shot) mode – The 555 operates as a "one-shot" pulse generator. Applications include: timers, missing pulse detection, bounce-free switches, touch switches, frequency dividers, triggered measurement of resistance or capacitance, PWM, etc. Bistable (latch) mode – The 555 operates as a set-reset latch. Applications include: switch debouncing. Schmitt trigger (inverter) mode – the 555 operates as a Schmitt trigger inverter gate. Application: Converts a noisy input into a clean digital output.
Astable
+ Astable mode examples with common values Frequency C R1 R2 Duty cycle 0.1Hz (+0.048%) 100μF 8.2kΩ 68kΩ 52.8% 1Hz (+0.048%) 10μF 8.2kΩ 68kΩ 52.8% 10Hz (+0.048%) 1μF 8.2kΩ 68kΩ 52.8% 100Hz (+0.048%) 100nF 8.2kΩ 68kΩ 52.8% 1kHz (+0.048%) 10nF 8.2kΩ 68kΩ 52.8% 10kHz (+0.048%) 1nF 8.2kΩ 68kΩ 52.8% 100kHz (+0.048%) 100pF 8.2kΩ 68kΩ 52.8%
In the astable configuration, the 555 timer puts out a continuous stream of rectangular pulses having a specific period.
The astable configuration is implemented using two resistors, and and one capacitor . The threshold and trigger pins are both connected to the capacitor; thus they have the same voltage.
Its repeated operating cycle (starting with the capacitor uncharged) is:
Since the capacitor's voltage will be below VCC, the trigger pin causes the 555's internal latch to change state, causing OUT to go high and the internal discharge transistor to cut-off. Since the discharge pin is no longer short-circuited to ground, the capacitor starts charging via current from Vcc through the resistors and . Once the capacitor charge reaches Vcc, the threshold pin causes the 555's internal latch to change state, causing OUT to go low and the internal discharge transistor to go into saturation (maximal-conductivity) mode. This discharge transistor provides a discharge path, so the capacitor starts discharging through . Once the capacitor's voltage drops below VCC, the cycle repeats from step 1.
During the first pulse, the capacitor charges from 0 V to VCC, however, in later pulses, it only charges from VCC to VCC. Consequently, the first pulse has a longer high time interval compared to later pulses. Moreover, the capacitor charges through both resistors but only discharges through , thus the output high interval is longer than the low interval. This is shown in the following equations:
The output high time interval of each pulse is given by:
The output low time interval of each pulse is given by:
Hence, the frequency of the pulse is given by:
and the duty cycle is given by:
where is the time in seconds, is the resistance in ohms, is the capacitance in farads, and is the natural log of 2 constant.
Resistor requirements: Minimum resistance - it is recommended that 5 kiloohm be the minimum resistance for , but this doesn't mean reasonable lower values can't be used in certain applications.