An Answer To Reset (ATR) is a message output by a contact Smart Card conforming to ISO/IEC 7816 standards, following electrical reset of the card's chip by a card reader. The ATR conveys information about the communication parameters proposed by the card, and the card's nature and state.
By extension, ATR often refers to a message obtained from a Smart Card in an early communication stage; or from the card reader used to access that card, which may transform the card's message into an ATR-like format (this occurs e.g. for some PC/SC card readersSection 3.2 in OMNIKEY Contactless Smart Card Readers Developer Guide when accessing an ISO/IEC 14443 Smart Card).
The presence of an ATR is often used as a first indication that a Smart Card appears operative, and its content examined as a first test that it is of the appropriate kind for a given usage.
Contact Smart Cards communicate over a signal named Input/Output (I/O) either synchronously (data bits are sent and received at the rhythm of one per period of the clock supplied to the card on its CLK signal) or asynchronously (data bits are exchanged over I/O with another mechanism for bit delimitation, similar to traditional asynchronous serial communication). The two modes are exclusive in a given communication session, and most cards are built with support for a single mode. Microprocessor-based contact Smart Cards are mostly of the asynchronous variety, used for all Subscriber Identity Modules (SIM) for mobile phones, those bank cards with contacts that conform to EMV specifications, all contact Java Cards, and Smart Cards for pay television. Memory-only cards are generally of the synchronous variety.
ATR under asynchronous and synchronous transmission have entirely different form and content. The ATR in asynchronous transmission is precisely normalized (in order to allow interoperability between cards and readers of different origin), and relatively complex to parse.
Some Smart Cards (mostly of the asynchronous variety) send different ATR depending on if the reset is the first since power-up (Cold ATR) or not (Warm ATR).
Note: Answer To Reset should not be confused with ATtRibute REQuest (ATR_REQ) and ATtRibute RESponse (ATR_RES) of NFC, also abbreviated ATR.ISO/IEC 18092:2004 — Information technology — Telecommunications and information exchange between systems — Near Field Communication — Interface and Protocol (NFCIP-1) ATR_RES conveys information about the communication parameters supported, as does Answer To Reset, but its structure is different.
ATR in asynchronous transmission
The standard defining the ATR in asynchronous transmission is ISO/IEC 7816-3.ISO/IEC 7816-3:2006 — Identification cards — Integrated circuit cards — Part 3: Cards with contacts — Electrical interface and transmission protocols (partial preview) Subsets of the full ATR specification are used for some Smart Card applications, e.g. EMV. , EMV 4.3 Integrated Circuit Card Specifications for Payment Systems — Book 1 — Application Independent ICC to Terminal Interface Requirements
Physical form and timing at the card/reader interface
In asynchronous transmission, the ATR is transmitted by a card to a reader as characters, encoded as bits over the contact designated I/O (C7), with a nominal bit duration denoted Elementary Time Unit (ETU), equal during the whole ATR to 372 periods of the clock signal supplied by the reader on the CLK (C3) contact. The I/O line is by default at a H state (the highest voltage of two logic levels), and a transition to L state, denoted leading edge, defines the start of a character. The leading edge of the first character occurs between 400 and 40 000 clock cycles after the reader changed the RST (C2) contact from L to H.
Each characters comprises a start bit at L state, 8 data bits, 1 parity bit, followed (absent error) by a delay at the H state (a high voltage on I/O) such that the leading edge of characters in the ATR is at least 12 ETU, with maximum designated Waiting Time WT = 9 600 ETU during the whole ATR (Eurocard MasterCard Visa specifications add that the reader should tolerate 10 800 ETU, that is 5% more). The value of the byte encoded by a character is defined according to conventions determined by the first character of the ATR, designated TS.
The end of the physical ATR between card and reader can be determined by the reader using analysis on the fly of the values of TS, T0, and any TDi (see below), or/and on the basis of WT. The later method incurs an extra delay (about 0.8 s at the maximum clock frequency of 5 MHz applicable during ATR). EMV (but not ISO/IEC 7816-3) also allows the reader to consider that the ATR must be over after 20 160 ETU (about 1.5 s at 5 MHz) counted from the leading edge of TS.
Note: When communicating in asynchronous mode with an ISO/IEC 7816-3 contact Smart Card using a serial interface device operating per direct convention (such as a standard UART), it can be set to 8 bits, 1 even parity bit, 2 stop bits (sometime negotiable to 1, see TC1); during the ATR, the baud rate should be 1/372 of the clock frequency received by the card (corresponding to an ETU of 372 clock cycles). There will normally be no parity error or framing error. The first byte received is if the card operates in direct convention, if the cards operates in inverse convention, in which case the polarity and order of all 8 bits of each byte going through the serial interface device should be reversed, which in particular will change the first byte to .
Historical note: provision for cards that use an internal clock source and a fixed ETU of 1/9 600 second during ATR existed in ISO/IEC 7816-3:1989, and was removed from the 1997 edition onwards.
General structure
The ATR proceeds in five steps: initial character TS; format byte T0; interface bytes TAi, TBi, TCi, TDi (optionals, variable number); historical bytes Ti (optionals, up to 15), and the check byte TCK (optional). There are a total of 2 to 33 characters including TS. Name Defines Encodes Present when TS Bit order and polarity (always) T0 Number of Ti, presence of TA1..TD1 K in [0..15] (always) TA1 Maximum clock frequency, proposed bit duration FI ↦ Fi and fmax; DI ↦ Di 5th bit of T0 is TB1 Deprecated: VPP requirements PI1 ↦ P, II ↦ I 6th bit of T0 is TC1 Extra delay between bytes required by card N ↦ EGT ↦ GT 7th bit of T0 is TD1 First offered transmission protocol, presence of TA2..TD2 T in [0..14] 8th bit of T0 is TA2 Specific protocol and parameters to be used after the ATR T in [0..14] 5th bit of TD1 is TB2 Deprecated: VPP precise voltage requirement PI2 ↦ P 6th bit of TD1 is TC2 Maximum waiting time for protocol T = 0 WI ↦ WT 7th bit of TD1 is TD2 A supported protocol or more global parameters, presence of TA3..TD3 T in [0..15] 8th bit of TD1 is TAi For T = 1 [#]: maximum block size the card can receiveIf T = 15 [#]: supported supply voltages and low power modes IFSCX; Y 5th bit of TDi-1 is TBi For T = 1 [#]: maximum delays between charactersIf T = 15 [#]: use of SPU contact C6 CWI ↦ CWT; BWI ↦ BWT 6th bit of TDi-1 is TCi For T = 1 [#]: type of error detection code used 7th bit of TDi-1 is TDi A supported protocol or more global parameters, presence of TAi+1..TDi+1 T in [0..15] 8th bit of TDi-1 is T1 The format of historical bytes Ti K ≥ 1 Ti Historical bytes indicating operating characteristics, per ISO/IEC 7816-4when T1 is , or , K ≥ i TCK Allow detection of accidental transmission error(the XOR of bytes T0 to TCK is normally zero) T in any of theTDi bytes is not 0 RFU Reserved for Future Use
[#] The signification given is assuming i > 2, and i-1 is the only j with 1 < j < i such that TDj encodes the stated value of T. When that T is in range [0..14], the signification of the byte applies only to the corresponding protocol (specific byte). When that T = 15, the signification applies regardless of protocol (global byte).
The initial character TS is always physically present, but is excluded of the Answer-to-Reset in the definition given by ISO/IEC 7816-3:2006: the value of the byte string (at most 32 bytes) encoded in the sequence of characters following the initial character TS. ISO/IEC 7816-4:2005 concurs, (archived copy), ISO/IEC 7816-4:2005 (Identification cards — Integrated circuit cards — Part 3: Cards with contacts — Organization, security and commands for interchange), note in section 7.4.2 stating that TS is a character or synchronization pattern, not a byte. However practice (in PC/SC, EMV, ETSI, and Calypso at least) is still to consider that TS is part of the ATR, as it was in ISO/IEC 7816-3:1997 and former. In particular, the ATR returned by PC/SC card readers and software stacks includes TS as the first byte, with value or .
Initial character TS
The initial character TS encodes the convention used for encoding of the ATR, and further communications until the next reset. In direct [resp. inverse] convention, bits with logic value are transferred as a High voltage (H) [resp. a Low voltage (L)]; bits with logic value are transferred as L [resp. H]; and least-significant bit of each data byte is first (resp. last) in the physical transmission by the card.
For direct convention, TS is and encodes the byte .
For inverse convention, TS is and encodes the byte .
[represents the idle (High, Mark) state of the I/O line. The 8 data bits are shown in italic. ]
Bits in bytes following TS in the ATR, and further communications until the next reset, are numbered 1st to 8th from low-order to high-order, and their value noted or, regardless of the chronological order and electrical representation, defined by TS. The bit following the 8 data bits in these bytes is an even parity bit, that is such that there's an even number of bits (H or L according to the direct or inverse convention defined by TS) among the 8 data bits and the parity bit.
TS also allows the card reader to confirm or determine the ETU, as one third of the delay between the first and second H-to-L transition in TS. This is optional, and the principal definition of ETU in the ATR of standard-compliant asynchronous Smart Cards is 372 periods of the clock received by the card.
Format byte T0
The Format byte T0 encodes in its 4 low-order bits (4th MSbit to 1st LSbit) the number K of historical bytes Ti, in range [0..15].
It also encodes in its 4 high-order bits the presence of at most 4 other interface bytes: TA1 (resp. TB1, TC1, TD1) follow, in that order, if the 5th (resp. 6th, 7th, 8th) bit of T0 is.
Interface bytes TAi, TBi, TCi, TDi
Interface bytes TA1, TB1, TC1, TD1, TA2, TB2, TC2, TD2, TA3, TB3, .. are all optional, and encode communication parameters and protocols that the card propose to use.
Interface bytes come in three kinds: global interface bytes apply to all protocols; specific interface bytes apply to a specific protocol; and structural interface bytes introduce further interface bytes, and protocols.
Interface byte TA1
Interface byte TA1, if present, is global, and encodes the maximum clock frequency fmax supported by the card, and the number of clock periods per ETU that it suggests to use after the ATR, expressed as the ratio Fi/Di of two integers. When TA1 is absent, it's assumed default value is , corresponding to fmax = 5 MHz, Fi = 372, Di = 1.
The 4 low-order bits of TA1 (4th MSbit to 1st LSbit) encode Di as: 4th to 1st bits Di RFU 1 2 4 8 16 32 64(#) 12 20 RFU RFU RFU RFU RFU RFU (#) This was RFU in ISO/IEC 7816-3:1997 and former. Some card readers or drivers may erroneously reject cards using this value (or other RFU). Some PC/SC readers, as a workaround to said driver behavior, clear the 1st bit of TA1 when its 4 low-order bits encode 7, and accordingly adjust TCK (if present), unless they have received a special command.
The 4 high-order bits of TA1 (8th MSbit to 5th LSbit) encode fmax and Fi as: