The following is a list of Intel CPU microarchitectures. Intel has produced many generations of CPU microarchitectures since the 1970s, spanning x86 processors for desktop, mobile, and server markets. Additional details about Intel's manufacturing and architecture strategy can be found in Intel's tick–tock model and the process–architecture–optimization model, which describe how Intel historically alternated between shrinking manufacturing processes and introducing new architectures. See also Template:Intel processor roadmap for planned future architectures.

x86 microarchitectures

+x86 microarchitectures Year Micro­architecture Pipeline stages Maxclock(MHz) Process node 1978 8086 (8086, 8088) 2 5 3000 nm 1982 186 (80186, 80188) 2 25 1982 286 (80286) 3 25 1500 nm 1985 386 (80386) 6Rant, Jon; "Extending the Legacy of Leadership: The 80386 Arrives", Intel Corporation, Special 32-Bit Issue Solutions, November/December 1985, page 2 33 1989 486 (80486) 5 100 1000 nm 1993 P5 (Pentium) 5 200 800, 600, 350 nm 1995 P6 (Pentium Pro, Pentium II) 14 (17 with load & store/retire) 450 500, 350, 250 nm 1997 P5 (Pentium MMX) 6 233 350 nm 1999 P6 (Pentium III) 12 (15 with load & store/retire) 1400 250, 180, 130 nm 2000 NetBurst (Pentium 4)(Willamette) 20 unified with branch prediction 2000 180 nm 2002 NetBurst (Pentium 4)(Northwood, Gallatin) 3466 130 nm 2003 Pentium M (Banias, Dothan)Enhanced Pentium M (Yonah) 10 (12 with fetch/retire) 2333 130, 90, 65 nm 2004 NetBurst (Pentium 4, Pentium D)(Prescott) 31 unified with branch prediction 3800 90, 65 nm 2006 Intel Core 12 (14 with fetch/retire) 3000 65 nm 2007 Penryn (die shrink) 3333 45 nm 2008 Nehalem 20 unified (14 without miss prediction) 3600 Bonnell 16 (20 with prediction miss) 2100 2010 Westmere (die shrink) 20 unified (14 without miss prediction) 3866 32 nm 2011 Saltwell (die shrink) 16 (20 with prediction miss) 2130 Sandy Bridge 14 (16 with fetch/retire) 4000 2012 Ivy Bridge (die shrink) 4100 22 nm 2013 Silvermont 14–17 (16–19 with fetch/retire) 2670 Haswell 14 (16 with fetch/retire) 4400 2014 Broadwell (die shrink) 3700 14 nm 2015 Airmont (die shrink) 14–17 (16–19 with fetch/retire) 2640 Skylake 14 (16 with fetch/retire) 5300 2016 Goldmont 20 unified with branch prediction 2600 2017 Goldmont Plus 20 unified with branch prediction (?) 2800 2018 Palm Cove 14 (16 with fetch/retire) 3200 10 nm 2019 Sunny Cove 12–19 (misprediction) 4100 2020 Tremont 20 unified 3300 Willow Cove 12 unified 5300 2021 Cypress Cove 12 unified 5300 14 nm Golden Cove 12 unified 5500 Intel 7 Gracemont 20 unified with misprediction penalty 4300 2022 Raptor Cove 12 unified 62002023 Redwood Cove 10 unified Intel 4, Intel 3 Crestmont Intel 4, TSMC N6, Intel 32024 Lion Cove 10 unifiedTSMC N3B Skymont 16 unified2026 Cougar Cove Intel 18A Panther Cove Darkmont Coyote Cove Arctic Wolf 2027 Griffin Cove Note: Atom/Power efficient microarchitectures are in Italic

16-bit

8086 first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80. The 8088 version, with an 8-bit bus, was used in the original IBM Personal Computer. 186 included a DMA controller, interrupt controller, timers, and chip select logic. A small number of additional instructions. The 80188 was a version with an 8-bit bus. 286 first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3 to 4 over 8086. Included instructions relating to protected mode. The 80286 had a 24-bit address bus.

32-bit (IA-32)

i386 first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions. i486 Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions. P5 original Pentium microprocessors, first x86 processor with super-scalar architecture and branch prediction. P6 used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, RISC μop decode scheme, integrated register renaming and out-of-order execution. Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. Added 36-bit physical memory addressing, "Physical Address Extension (PAE)". Pentium M: updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to support micro-op fusion and smart cache. Enhanced Pentium M: updated, dual core version of the Pentium M microarchitecture used in the first Intel Core microprocessors, first x86 to have shadow register architecture and speed step technology. NetBurstcommonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Used in Pentium 4, Pentium D, and some Xeon microprocessors. Very long pipeline. The Prescott was a major architectural revision. Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for the NX (No eXecute) bit to implement executable-space protection.

64-bit (x86-64)

Core reengineered P6-based microarchitecture used in Intel Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file. Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, SSE4.1 instructions, support for XOP and F/SAVE and F/STORE instructions, enhanced register alias table and larger integer register file. Nehalem released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions, SSE4.2. Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.

Sandy Bridge32 nm microarchitecture, released January 9, 2011. Formerly called Gesher but renamed in 2007. First x86 to introduce 256 bit AVX instruction set and implementation of YMM registers. Ivy Bridge: successor to Sandy Bridge, using 22 nm process, released in April 2012.

Haswell 22 nm microarchitecture, released June 3, 2013. Added a number of new instructions, including AVX2 and FMA. Broadwell: 14 nm derivative of the Haswell microarchitecture, released in September 2014. Three-cycle FMUL latency, 64 entry scheduler. Formerly called Rockwell.

Skylake14 nm microarchitecture, released August 5, 2015. Kaby Lake: successor to Skylake, released in August 2016, broke Intel's tick-tock schedule due to delays with the 10 nm process. Amber Lake: ultra low power, mobile-only successor to Kaby Lake, using 14+ nm process, released in August 2018 (no architecture changes) Whiskey Lake: mobile-only successor to Kaby Lake Refresh, using 14++ nm process, released in August 2018 (has hardware mitigations for some vulnerabilities) Skylake-X: high-end desktop, workstation and server microarchitecture, released on June 19, 2017 (HEDT), July 11, 2017 (SP) and August 29, 2017 (W). Introduces support for AVX-512 instruction set. Coffee Lake: successor to Kaby Lake, using 14++ nm process, released in October 2017 Cascade Lake: server and high-end desktop successor to Kaby Lake-X and Skylake-X, using 14++ nm process, released in April 2019 Comet Lake: successor to Coffee Lake, using 14++ nm process, released in August 2019 Cooper Lake: server-only, optimized for AI oriented workloads using bfloat16, with limited availability only to Intel priority partners, using 14++ nm process, released in 2020

Palm Cove Originally meant to be successor to Skylake, but cancelled after releasing just one chip. Includes the AVX-512 instruction set. Cannon Lake: mobile-only successor of Kaby Lake, using Intel's 10 nm process, first and only microarchitecture to implement the Palm Cove core, released in May 2018. Formerly called Skymont, discontinued in December 2019. Starting with Cannon Lake, Intel has changed their microarchitecture naming scheme, decoupling core codenames from CPU codenames.

Sunny CoveSuccessor to the Palm Cove core, first non-Atom core to include hardware acceleration for SHA hashing algorithms. Ice Lake: low power, mobile-only successor to Whiskey Lake, using 10 nm process, released in September 2019 Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Sunny Cove is used in the singular performance core (P-core) of Lakefield processors. AVX and more advanced instruction sets are disabled due to the E-core not supporting them. Ice Lake-SP: server-only successor to Cascade Lake, using 10 nm process, released in April 2021

Cypress Cove Backport of Sunny Cove to Intel's 14 nm process Rocket Lake: Successor to Comet Lake, using Intel's 14++ nm process, released on March 30, 2021

Willow CoveSuccessor to the Sunny Cove core, includes new security features and redesigns the cache subsystem. Tiger Lake: successor to Ice Lake, using Intel's 10 nm SuperFin (10SF) process, released in Q4 2020

Golden CoveSuccessor to the Willow Cove core, includes improvements to performance and power efficiency. Also includes new instructions. Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake; uses Intel 7 process (previously known as 10ESF), released on November 4, 2021. Golden Cove is used in P-cores of Alder Lake processors. Sapphire Rapids: server and workstation-only, successor to Ice Lake-SP, manufactured on Intel 7 process, released on January 10, 2023. Introduces AMX.

Raptor CoveA refresh of Golden Cove with increased L2 and L3 caches and core clocks. Raptor Lake: successor to Alder Lake with increased cache sizes, core clocks and the number of E-cores, released on October 20, 2022. Manufactured using Intel 7 process. Raptor Cove is used in the P-cores while the E-cores are still implemented using Gracemont microarchitecture. Emerald Rapids: successor to Sapphire Rapids, server- and workstation-only. Fifth-generation Xeon Scalable server processors based on the Intel 7 node.

x86 ULV (Atom)

Bonnell 45 nm, low-power, in-order microarchitecture for use in Atom processors. Saltwell: 32 nm shrink of the Bonnell microarchitecture.

Silvermont 22 nm, out-of-order microarchitecture for use in Atom processors, released on May 6, 2013. Airmont: 14 nm shrink of the Silvermont microarchitecture.

Goldmont 14 nm Atom microarchitecture iteration after Silvermont but borrows heavily from Skylake processors (e.g., GPU), released in April 2016. Goldmont Plus: successor to Goldmont microarchitecture, still based on the 14 nm process, released on December 11, 2017.

Tremont10 nm Atom microarchitecture iteration after Goldmont Plus. Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Tremont is used in efficiency cores (E-cores) of Lakefield processors. Jasper Lake: Celeron and Pentium Silver desktop and mobile processors, released in Q1 2021. Elkhart Lake: embedded processors targeted at IoT, released in Q1 2021.

Gracemont Intel 7 process Atom microarchitecture iteration after Tremont. First Atom class core with AVX and AVX2 support. Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake, released on November 4, 2021. Gracemont is used in E-cores of Alder Lake processors. Raptor Lake: a refresh of Alder Lake, released on October 20, 2022.

x86 MIC (Many Integrated Core)

Larrabee (cancelled 2010)