The PowerPC 600 family was the first family of PowerPC processors built. They were designed at the Somerset facility in Austin, Texas, jointly funded and staffed by engineers from IBM and Motorola as a part of the AIM alliance. Somerset was opened in 1992 and its goal was to make the first PowerPC processor and then keep designing general purpose PowerPC processors for personal computers. The first incarnation became the PowerPC 601 in 1993, and the second generation soon followed with the PowerPC 603, PowerPC 604 and the 64-bit PowerPC 620.
Family CPUPipeline stagesFeatures60143 execution units, static branch prediction. SMP support.60345 execution units, branch prediction. No SMP.6046Superscalar, out-of-order execution, 6 execution units. SMP support.6205Out-of-order execution- SMP support.
PowerPC 601
The PowerPC 601 was the first generation of microprocessors to support the basic 32-bit PowerPC instruction set. The design effort started in earnest in mid-1991 and the first prototype chips were available in October 1992. The first 601 processors were introduced in an IBM RS/6000 workstation in October 1993 (alongside its more powerful multichip cousin IBM POWER2 line of processors) and the first Apple Power Macintoshes on March 14, 1994. The 601 was the first advanced single-chip implementation of the POWER/PowerPC architecture designed on a crash schedule to establish PowerPC in the marketplace and cement the AIM alliance. In order to achieve an extremely aggressive schedule while including substantially new functionality (such as substantial performance enhancements, new instructions and importantly POWER/PowerPC's first symmetric multiprocessing (SMP) implementation) the design leveraged a number of key technologies and project management strategies. The 601 team leveraged much of the basic structure and portions of the IBM RISC Single Chip (RSC) processor, but also included support for the vast majority of the new PowerPC instructions not in the POWER instruction set. While nearly every portion of the RSC design was modified, and many design blocks were substantially modified or completely redesigned given the completely different unified I/O bus structure and SMP/memory coherency support. New PowerPC changes, leveraging the basic RSC structure was very beneficial to reducing the uncertainty in chip area/floorplanning and timing analysis/tuning. Worth noting is that the 601 not only implemented substantial new key functions such as SMP, but it also acted as a bridge between the POWER and the future PowerPC processors to assist IBM and software developers in their transitions to PowerPC. From start of design to tape-out of the first 601 prototype was just 12 months in order to push hard to establish PowerPC on the market early.
60x bus In order to help the effort to rapidly incorporate the 88110 bus architecture to the 601 for the benefit of the alliance and its customers, Motorola management provided not only the 88110 bus architecture specifications, but also a handful of 88110 bus-literate designers to help with the 60x bus logic implementation and verification. Given the Apple system design team was familiar with the I/O bus structure from Motorola's 88110 and this I/O bus implementation was well defined and documented, the 601 team adopted the bus technology to improve time to market. The bus was renamed the 60x bus once implemented on the 601. These Motorola (and a small number of Apple) designers joined over 120 IBM designers in creating the 601.
Using the 88110 bus as the basis for the 60x bus helped schedules in a number of ways. It helped the Apple Power Macintosh team by reducing the amount of redesign of their support ASICs and it reduced the amount of time required for the processor designers and architects to propose, document, negotiate, and close a new bus interface (successfully avoiding the "Bus Wars" expected by the 601 management team if the 88110 bus or the previous RSC buses had not been adopted). Worthy to note is that accepting the 88110 bus for the benefit of Apple's efforts and the alliance was at the expense of the first IBM RS/6000 system design team's efforts who had their support ASICs already implemented around the RSC's totally different bus structure.
This 60x bus later became a fairly long lived basic interface for the many variants of the 601, 603, 604, G3, G4 and Motorola/Freescale PowerQUICC processors.
Design
The chip was designed to suit a wide variety of applications and had support for external L2 cache and symmetric multiprocessing. It had four functional units, including a floating-point unit, an integer unit, a branch unit and a sequencer unit. The processor also included a memory management unit. The integer pipeline was four stages long, the branch pipeline two stages long, the memory pipeline five stages long, and the floating-point pipeline six stages long.
First launched in IBM systems in the fall of 1993, it was marketed by IBM as the PPC601 and by Motorola as the MPC601. It operated at speeds ranging from 50 to 80 MHz. It was fabricated using a 0.6 μm CMOS process with four levels of aluminum interconnect. The die was 121 mm2 large and contained 2.8 million transistors. The 601 has a 32 KB unified L1 cache, a capacity that was considered large at the time for an on-chip cache. Thanks partly to the large cache it was considered a high performance processor in its segment, outperforming the competing Intel Pentium. The PowerPC 601 was used in the first Power Macintosh computers from Apple, and in a variety of RS/6000 workstations and SMP servers from IBM and Groupe Bull.
IBM was the sole manufacturer of the 601 and 601+ microprocessors in its Burlington, Vermont and East Fishkill, New York production facilities. The 601 used the IBM CMOS-4s process and the 601+ used the IBM CMOS-5x process. An extremely small number of these 601 and 601+ processors were relabeled with Motorola logos and part numbers and distributed through Motorola.
PowerPC 601 Microprocessor, lecture by Keith Diefendorff
PowerPC 601v
An updated version, the PowerPC 601v or PowerPC 601+, operating at 90 to 120 MHz was introduced in 1994. It was fabricated in a newer 0.5 μm CMOS process with four levels of interconnect, resulting in a die measuring 74 mm2. The 601+ design was remapped from CMOS-4s to CMOS-5x by an IBM-only team. To avoid time-to-market delays from design tool changes and commonizing fab groundrules, both the 601 and 601+ were designed with IBM EDA tools on IBM systems and were fabricated in IBM-only facilities.
PowerPC 603
The PowerPC 603 was the first processor implementing the complete 32-bit PowerPC Architecture as specified. Introduced in 1994, it was an advanced design for its day, being one of the first microprocessors to offer dual issue (up to three with branch folding) and out-of-order execution combined with low power consumption of 2.2 W and a small die of 85 mm2.Pham et al., "A 3.0 W 75 SPECint92 85 SPECfp92 Superscalar RISC Microprocessor", ISSC Digest Of Technical Papers, pp. 212–213, Feb. 1994.Burgess et al., "The PowerPC 603 Microprocessor: A High Performance, Low Power, Superscalar RISC Microprocessor", Proceedings of COMPCON '94, Feb. 1994.Gary et al., "The PowerPC 603 Microprocessor: A Low-Power Design For Portable Applications", Proceedings of COMPCON '94, Feb. 1994.Gerosa et al., "A 2.2 W, 80 MHz Superscalar RISC Microprocessor", IEEE Journal of Solid-State Circuits, vol. 29, pp. 1440–1454, Dec. 1994. It was designed to be a low cost, low power processor for portable applications. One of the main features was power saving functions (doze, nap and sleep mode) that could dramatically reduce power requirements, drawing only 2 mW in sleep mode. The 603 has a four-stage pipeline and five execution units: integer unit, floating-point unit, branch prediction unit, load/store unit and a system registry unit. It has separate 8 KB L1 caches for instructions and data and a 32/64 bit 60x memory bus, reaching up to 120 MHz at 3.8 V. The 603 core did not have hardware support for SMP.
The PowerPC 603 had 1.6 million transistors and was fabricated by IBM and Motorola in a 0.5 μm CMOS process with four levels of interconnect. The die was 85 mm2 large drawing 2.2 W at 80 MHz. The 603 architecture is the direct ancestor to the PowerPC 750 architecture, marketed by Apple as the PowerPC "G3".
The 603 was intended to be used for portable Apple Macintosh computers but could not run 68K emulation software with performance Apple considered adequate, due to the smaller processor caches. As a result, Apple chose to only use the 603 in its low-cost desktop Performa line. This caused the delay of the Apple PowerBook 5300 and PowerBook Duo 2300, as Apple chose to wait for a processor revision. Apple's use of the 603 in the Performa 5200 line led to the processor getting a poor reputation. Aside from the issue of 68K emulation performance, the Performa machines shipped with a variety of design flaws, some of them severe, related to other aspects of the computers' design, including networking performance and stability, bus problems (width, speed, contention, and complexity), ROM bugs, and hard disk performance. None of the problems of the 5200 line, aside from 68K emulation performance, were inherently due to the 603. Rather, the processor was retrofitted to be used with 68K motherboards and other obsolete parts. The site Low End Mac rates the Performa 5200 as the worst Mac of all-time. The 603 found widespread use in different embedded appliances.
PowerPC 603e The performance issues of the original 603 were addressed with the PowerPC 603e. Its level 1 cache was increased to 16 KB four-way set-associative instruction and data caches, and clock speeds initially reached 200 MHz. The 603e contained 2.6 million transistors on a 98 mm2 die. It was used in systems including the BeBox, IBM ThinkPad 800 series, accelerator cards produced by Phase5 for the Amiga, digital oscilloscopes manufactured by LeCroy, the Iridium satellite constellation, and the Mark 54 Lightweight Torpedo.LeCroy 1998 Test & Measurement Products Catalog, TMCAT98 0498LeCroy 2001 Test and Measurement Products Catalog
PowerPC 603ev
A revised version of the 603e manufactured on a 350 nm process, the PowerPC 603ev, increased maximum clock speeds to 300 MHz while reducing the die size to 78 mm2. The 603ev retained the 603e's 2.6 million-transistor design and drew up to 6 W at 300 MHz. The 603ev became the first mainstream desktop PowerPC processor to reach 300 MHz, appearing in the Power Macintosh 6500.
Freescale G2 The PowerPC 603e core, renamed G2 by Freescale Semiconductor, is the basis for many embedded PowerQUICC II processors, and, as such, it keeps on being developed. Freescale's PowerQUICC II SoC processors bear the designation MPC82xx, and come in a variety of configurations reaching 450 MHz.
PowerPC e300
Freescale enhanced the 603e core, calling it e300, in the PowerQUICC II Pro embedded processors. Larger 32/32 KB L1 caches and other performance enhancing measures were added. Freescale's PowerQUICC II Pro SoC processors bear the designation MPC83xx, and come in a variety of configurations reaching speeds up to 667 MHz. The e300 is also the core of the MPC5200B SoC processor that is used in the small EFIKA computer.
PowerPC 604
The PowerPC 604 was introduced in December 1994 alongside the 603 and was designed as a high-performance chip for workstations and entry-level servers and as such had support for symmetric multiprocessing in hardware. The 604 was used extensively in Apple's high-end systems and was also used in Macintosh clones, IBM's low-end RS/6000 servers and workstations, Amiga accelerator boards, and as an embedded CPU for telecom applications.