The Elliott 803 is a small, medium-speed transistor digital computer which was manufactured by the British company Elliott Brothers in the 1960s. About 211 were built.
History
The 800 series began with the 801, a one-off test machine built in 1957. The 802 was a production model but only seven were sold between 1958 and 1961. The short-lived 803A was built in 1959 and first delivered in 1960; the 803B was built in 1960 and first delivered in 1961.
Over 200 Elliott 803 computers were delivered to customers, at a unit price of about £29,000 in 1960 (roughly ). Most sales were of the 803B version with more parallel paths internally, larger memory and hardware floating-point operations.
One model was used to interface with a facsimile of the American Field Artillery Digital Automatic Computer FADAC for trials by the British Royal Artillery in the production of howitzer firing data. After successful trials the Army went on to commission the General Electric Company GEC to produce the Field Artillery Computer System Face for the Royal Artillery.
The Elliott 803 was the computer used in the ISI-609, the world's first process or industrial control system, wherein the 803 was a data logger. It was used for this purpose at the US's first dual-purpose nuclear reactor, the N-Reactor.
A significant number of British universities had an Elliott 803.
Elliott subsequently developed (1963) the much faster, software compatible, Elliott 503.
Two complete Elliott 803 computers survive. One is owned by the Science Museum in London but it is not on display to the public. The second is owned by The National Museum of Computing (TNMoC) at Bletchley Park, is fully functional, and can regularly be seen in operation by visitors to that museum.Elliott 803 news, more tidbits from the archive and several generous donations to boot , 2010-09-19, The National Museum of Computing
Hardware description
The 803 is a transistorised, bit-serial machine; the 803B has more parallel paths internally. It uses ferrite magnetic-core memory in 4096 or 8192 words of 40 bits, comprising 39 bits of data with parity. The central processing unit (CPU) is housed in one cabinet with a height, width, and depth, of . Circuitry is based on printed circuit boards with the circuits being rather simple and most of the signalling carried on wires. There is a second cabinet about half the size used for the power supply, which is unusually based on a large nickel–cadmium battery with charger, an early form of uninterruptible power supply. A third cabinet (the same size as the power cabinet) holds the extra working store on machines with 8192 word stores. There is an operator's control console, Creed teleprinter and high-speed paper punched tape reader and punch for input/output, using 5-track Elliott telecode code, not Baudot. Tape is read at 500 characters per second and punched at 100 cps. The operator's console, about 60 inches long, allows low-level instructions to be entered manually to manipulate addresses and data and can start, stop and step the machine: there is a loudspeaker (pulsed by the top bit of the instruction register) which allows the operator to judge the status of a computation. The system requires air conditioning, drawing about 3.5 kW of power in a minimal configuration. A minimal installation weighed about .Weight of central processor (680), power unit (380 + 200 [battery charger]), paper tape station (450?), keyboard (66?):
Battery charger:
Optional mass storage is available on an unusual magnetic tape system based on standard 35 mm film stock coated with iron oxide (manufactured by Kodak). At the time this was in use by the film industry to record sound tracks. Elliott's factory at Borehamwood was close to the Elstree film studios which explains the use of the 35mm sprocketed media. The 1000-foot reels held 4096 blocks of 64 words per block (4096 x 64 x 39 = 10,223,616 bits, or the equivalent of about 1.3 megabytes).
Another unusual feature is the use of magnetic cores not only for memory but also as logic gates. These logic cores have 1, 2 or 3 input windings, a trigger (read) and an output winding. Depending on their polarity, current pulses in the input windings either magnetise the core or cancel each other out. The magnetised state of the core indicates the result of a boolean logic function. Two clock phases designated alpha and beta are used to trigger (reset to zero) alternate cores. A change from a one to a zero produces a pulse on the output winding. Cores which receive alpha trigger pulses (alpha cores) have inputs fed from gates which are triggered on the beta phase (beta cores). Transistors were expensive at the time and each logic gate requires only one to amplify the output winding pulse; however a single transistor drives the inputs of a small number of (typically 3) other cores. If more than 3 inputs are to be driven, up to two more transistors can be driven by each core.
Instruction set
Instructions and data are based on a 39-bit word length with binary representation in 2's complement arithmetic. The instruction set operates on a single address and single accumulator register, with an additional auxiliary register for double length integer multiply and divide. Although it is believed that the single length divide and square root instructions were only enabled in 803s destined for process control applications, the one remaining operational 803B has been found to have these instructions enabled, probably because it was used by a software house to develop real time and process control applications. An instruction is composed of a 6-bit function field (conventionally represented in octal) and a 13 bit address. This gives 64 instructions organised as 8 groups of 8 instructions. The 13-bit memory address field gives an addressable range of 8192 words. These 19-bit instructions are packed two to a word with an additional 39th bit between them, the so-called B-line or B digit (the term is a legacy from the Ferranti Mark 1 computer, where the A-line represented the accumulator and the B-line an instruction modifier, both stored on a Williams tube). Setting the B digit has the effect of adding the contents of the memory address of the first instruction to the second instruction at execution time, enabling indexing, indirect addressing, and other run-time instruction modifications. The bit time is 6 microseconds, jumps execute in 288 microseconds and simple arithmetic instructions in 576 microseconds. Floating-point operations take several milliseconds. IO is direct. Interrupts were not used by standard peripherals or documented in the programming guide.
In the following descriptions, A and N represent the accumulator and the literal address, a and n represent the (initial) contents of the accumulator and addressed store location, and a' and n' the resultant contents.
Instruction Groups 0 – 3
These are fixed point arithmetic with 4 different combinations of operand and result destination:
+ Groups 0 – 3 Fn Operation a' n' Fn Operation a' n' 00 Do nothing a n 01 Negate -a n 02 Replace & count n + 1 n 03 Collate a & n n 04 Add a + n n 05 Subtract a - n n 06 Clear zero n 07 Negate & add n - a n 10 Exchange n a 11 Exchange and negate -n a 12 Exchange and count n + 1 a 13 Write and collate a & n a 14 Write and add a + n a 15 Write and subtract a - n a 16 Write and clear zero a 17 Write, negate and add n - a a 20 Write a a 21 Write negatively a -a 22 Count in store a n + 1 23 Collate in store a a & n 24 Add into store a a + n 25 Negate store and add a a - n 26 Clear store a zero 27 Subtract from store a n - a 30 Replace n n 31 Replace and negate store n -n 32 Replace and count in store n n + 1 33 Replace and collate in store n a & n 34 Replace and add to store n a + n 35 Replace, negate store and add n a - n 36 Replace and clear store n zero 37 Replace and subtract from store n n - a
Instruction Group 4
Group 4 is conditional and unconditional jumps. Functions 40 – 43 jump to the first instruction of a pair, and 44 – 47 to the second. + Group 4 Fn Operation 40 Transfer to 1st instruction unconditionally 41 Transfer to 1st instruction if a is negative 42 Transfer to 1st instruction if a is zero 43 Transfer to 1st instruction if overflow set, and clear it 44 Transfer to 2nd instruction unconditionally 45 Transfer to 2nd instruction if a is negative 46 Transfer to 2nd instruction if a is zero 47 Transfer to 2nd instruction if overflow set, and clear it
Instruction Group 5
Group 5 is multiply, divide and shift instructions. Some of these use the 38-bit Auxiliary Register (AR – contents denoted by ar), which can be thought of as an extension of the accumulator at the least significant end. Multiplications and divisions regard a/ar as a signed fraction between -1 and one least significant bit less than +1. Despite the 803 Handbook saying "All odd functions in Group 5 clear the AR", function 57 does not clear it. + Group 5 Fn Operation 50 Arithmetic right shift a/ar N times 51 Logical right shift a N times, clear ar 52 Multiply a by n, result to a/ar 53 Multiply a by n, single length rounded result to a, clear ar 54 Arithmetic left shift a/ar N times 55 Logical left shift a N times, clear ar 56 Divide a/ar by n, single length quotient to a, clear ar 57 Copy ar to a, set sign bit zero, do NOT clear the ar
Instruction Group 6
Group 6 is floating-point instructions (if a floating-point unit is installed).
Floating-point numbers are represented in a 39-bit word or in the accumulator as (from most to least significant end): a 30 bit 2's complement signed mantissa a in the range ½ ≤ a < 1 or -1 ≤ a < -½ a 9 bit signed exponent b represented as a positive integer 0 ≤ (b+256) ≤ 511. Zero is always represented by all 39 bits zero.
Note that the test for zero and test for negative jump instructions are equally valid for floating-point. + Group 6 Fn Operation a' n' 60 Add n to a a + n n 61 Subtract n from a a - n n 62 Negate a and add n n - a n 63 Multiply a by n a * n n 64 Divide a by n a / n n 65 N = 4096: Convert fixed point integer in the accumulator to floating-point 65 N < 4096: Fast left (end round) shift N mod 64 places 66 (Spare) 67 (Spare) All these instructions clear the auxiliary register.
Instruction Group 7
Group 7 is input/output, with the exception of 73, which is used for subroutine linkage. There is a much more complete description of the Group 7 functions in the "Our Computer Heritage" link. + Group 7 Fn Operation 70 Read the keyboard number generator to the accumulator 71 Read one character from the tape reader and logically "or" it into the least significant 5 bits of the accumulator 72 Output to optional peripheral device such as the digital plotter: 73 Write the address of this instruction to location N 74 Send a character represented by N to the punch 75 Channel 2 function 76 Channel 2 function 77 Channel 2 function
Digital Plotter Control: Instruction Pen motion 72 7168 No motion 72 7169 EAST 72 7170 WEST 72 7172 NORTH 72 7176 SOUTH 72 7173 NORTH EAST 72 7174 NORTH WEST 72 7177 SOUTH EAST 72 7178 SOUTH WEST 72 7184 Pen Up 72 7200 Pen Down
Entry to a subroutine at address N is normally effected by the sequence: 73 LINK : 40 N The return address has been stored in a link location (typically the location before the start of the subroutine (e.g. N-1) )
and returns by using the sequence: 00 LINK / 40 1
Example program
By way of an example, the following is the Initial Instructions, hard-wired into locations 0 – 3, and used for loading binary code from paper tape into memory. In accordance with the 803 convention, it is written with two instructions on each line, representing the contents of one word. The colon or slash between them represent a B digit value of zero or one respectively. 0: 26 4 : 06 0 Clear loc'n 4; Clear A 1: 22 4 / 16 3 Increment loc 4; Store A in loc'n (3 + content of loc'n 4) & clear A