The TI-990 is a series of 16-bit minicomputers sold by Texas Instruments (TI) in the 1970s and 1980s. It served as a replacement for TI's earlier minicomputer systems, the TI-960 and the TI-980. The TI-990 features several unique innovations and was designed to be easier to program than its predecessors.
Among its core concepts is the ability to support multiprogramming using a software-switchable set of processor registers that allowed it to perform rapid context switches between programs. This is enabled through the use of register values stored in main memory that could be swapped by changing a single pointer.
TI later implemented the TI-990 in a single chip, the TMS9900, one of the first 16-bit microprocessors. Intended for use in low-end models of the TI-990, it retained the 990's memory-to-memory architecture. This chip was widely used in the TI-99/4A home computer, where aggressive cost-cutting measures presented significant performance disadvantages.
TI-990 models The TI-990 processors fell into several natural groups depending on the original design upon which they are based and which I/O bus they used.
All models support the Communications Register Unit (CRU) which is a serial bit addressable I/O bus. Also, supported on higher end models is the TILINE I/O bus which is similar to DEC's popular UNIBUS. The TILINE also supports a master/slave relationship that allowed multiple CPU boards in a common chassis with arbitration control.
CRU-only models The following models used the CRU as their principal bus: TI-990/9 — The original TTL implementation; 1974 TI-990/4 — TMS9900 microprocessor with 56 KB of memory
TILINE/CRU models The following models used the TILINE as their principal mass storage bus: TI-990/5 — TMS9900 microprocessor with 64 KB of memory TI-990/10 — TTL processor with memory mapping support to 2 MB of ECC memory; 1975 TI-990/10A — TMS99000 microprocessor with memory mapping support to 1 MB of memory TI-990/12 — Schottky TTL processor with memory mapping to 2 MB of ECC Memory, workspace caching, hardware floating point, extended mode instructions and writeable control store
Features Orthogonal instruction set The TI-990 series has a fairly orthogonal instruction set. The instruction formats allows for one-, two- and three-word instructions. The model 990/12 CPU allows for a four- word instruction with extended mode operations.
Workspaces In the TI-990 series, the general-purpose registers are stored in memory and are referred to through a hardware register called the Workspace Pointer. The concept behind the workspace is that main memory was based on the new semiconductor RAM chips that TI had developed and ran at the same speed as the CPU. This meant that it didn't matter if the "registers" were real registers in the CPU or stored in memory. When the Workspace Pointer is loaded with a memory address, that address is the origin of the registers.
There are only three hardware registers in the 990: the Workspace Pointer (WP), the Program Counter (PC) and the Status register (ST). A context switch entailed the saving and restoring of only the hardware registers.
Architectural details Addresses are 16-bit byte addresses, so the address space is 216 bytes (65,536 bytes or 32,768 words) large. The byte ordering in words is big endian.
There is no dedicated stack pointer register. Instead, branch instructions exist that save the program counter to a register (BL — Branch and Link), or change the register context (BLWP — Branch and Link Workspace Pointer, or XOP). The 16 hardware and 16 software interrupt vectors each consist of a pair of PC and WP values, so the register context switch is automatically performed by an interrupt as well. Stacks can be implemented atop either of these mechanisms.
Along with the typical single-bit flags seen in most processors, the status register contains a 4-bit interrupt mask. The value, 0 to 15, indicates the maximum interrupt that can be triggered. For instance, if interrupt 10 has been called, and interrupt 12 is triggered, the CPU checks this values, sees that 10 is running, and blocks the request.
+ TI-990 hardware registers 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 (bit position) PC 0 Program Counter WP 0 Workspace Pointer L> A> EQ C O P X PR MF MM OI CS Int Mask Status Register
There are 16 general-purpose "workspace registers". Several registers have defined purposes in many instructions. These are: R0 - shift counter, extended mode counter, Floating point Accumulator (FAC) most significant word R1 - FAC+2 (single precision) R2 - FAC+4 (double precision) R3 - FAC+6 (double precision) R11 - return linkage, or pointer to operand of XOP (privileged mode) R12 - CRU base address (privileged mode) R13 - Saved Workspace Pointer R14 - Saved Program Counter R15 - Saved Status Register
Addressing modes Most instruction operands are represented with an addressing mode and a general-purpose register used by that addressing mode. In these examples, Rn is a general-purpose register, 0 to 15. The addressing modes are:
CodeNameExampleDescription0nRegisterRnThe operand is in Rn1nIndirect register*RnRn contains the address of the operand2nIndexed@mem(Rn)Rn contains an index value to add to address mem, forming the address of the operand20SymbolicmemIf Rn is R0, direct memory addressing is specified. The address mem is used as the address of the operand.3nIndirect autoincrement*Rn+Rn contains the address of the operand, then increment Rn by data size
Instructions The 990/9, 990/4, and 990/5 instruction sets consisted of 69 instructions, the 990/10 had 72 instructions, the 990/10A had 77 instructions, and the 990/12 had 144 instructions.
For subroutine calls, the Branch and Load Workspace Pointer (BLWP) instruction loads new WP and PC values, then saves the values of WP, PC, and ST to (new) registers 13, 14, and 15 respectively. At the end of the subroutine, the Return Workspace Pointer (RTWP) restores these in reverse order. Using BLWP/RTWP, it is possible to nest subroutine calls despite the absence of a stack, however, the programmer needs to assign the appropriate register workspace explicitly.
The instruction set also contains a Branch and Link (BL) opcode that only saves PC to register 11 without changing WP. In this case, a branch instruction (B) using WR11 as the destination address can serve as the return opcode, but BL-type subroutines cannot be nested without the programmer taking actions to save the return address.
Then execute instruction "X" (eXecute) executes the instruction in a register or memory location. It can be used for debugging (as a breakpoint instruction), for creating indexed-opcode tables as used in byte-code interpreters and can also be used to perform a time critical I/O instruction during an interrupt. An example of its utility is shown in the code below where an interrupt is being serviced in a very encapsulated manner that would otherwise require many more instructions.
; THIS INTERRUPT SIMULATES DMA CONTROL ; ORGANISED AS FOLLOWS: ; ; R9 HOLDS CURRENT COMMAND, E.G. ; IOREAD(34B8H): STCR *R8+,BYTEWIDE ;BYTE WIDE FDC DATA READ ; IOWRITE(30B8H):LDCR *R8+,BYTEWIDE ;BYTE WIDE FDC DATA WRITE ; R8 HOLDS THE CURRENT DMA ADDRESS. ; R12 HOLDS THE CURRENT IO PORT - DATREG
INTDRQ X R9 ;CAN BE EITHER READ or WRITE RTWP
This common piece of code during the interrupt could be used by both I/O read and write commands. Similar methods could be employed in any debugging methods wanting to be used.
TI-990 series processors also support the eXtended OPeration (XOP) instruction. XOP is given a number in the range 0–15 as well as a source address. When invoked, the instruction will perform a context switch through one of sixteen vectors at predefined locations in memory. The XOP instruction also places the effective address of the source operand in register R11 of the new workspace. The context-saving feature of the XOP instruction can also be used as to implement inline debugging.
XOP is less flexible than a BLWP, as the transfer vectors have to be at fixed locations, but allows one source operand to be directly addressed rather than passed in a register or otherwise.
XOP can be used to implement a system call facility. In TI's DX10 operating system, XOP 15 invokes a system call. A programmer might define an assembler macro, for example SVC, which invokes XOP 15. Another use of XOP was to implement instructions in software which might be handled by dedicated hardware in future versions of the 990 minicomputer series. An example of such actions can be shown in the code below where a CALL function is implemented using and XOP 6 instruction. The beauty of this implementation of a CALL function using an XOP is that it is straightforward to add checks to determine if the stack overflowed, for example C R10,@2*R9(R13), where R9 points to the address of the stack limit.
; CALL SUBROUTINE ; DEFINE XOP: DXOP CALL,6 ; CALLING METHOD: CALL @SUBROUTINE_ADDRESS ; R10 <=> STACK POINTER
ED32 C2AD 0014 XOP6: MOV @2*R10(R13),R10 ;GET STACK POINTER ED36 064A DECT R10 ;DECREMENT STACK POINTER ED38 C68E MOV R14,*R10 ;PUSH RETURN PC ONTO STACK ED3A C38B MOV R11,R14 ;MOVE EA INTO R14 (PC) FOR CALL ED3C CB4A 0014 MOV R10,@2*R10(R13) ;UPDATE STACK POINTER ED40 0380 RTWP ;WE ARE NOW USING THE ORIGINAL WP
The 990/10 has a facility to allow specific XOP codes to use plug-in hardware. If the hardware is not present, the regular XOP trap is performed. This allowed for 15 attached devices on a system, although, device 15 is reserved in TI's operating systems for the Supervisor Call (SVC), through which user programs requested I/O and other operating systems services.
On the 990/12, if the writable control store is enabled, the XOP instruction would jump to microcode in the writable control store.
The instructions are grouped according to the instruction format. A format is defined by the layout of bit fields within the instruction word. The leftmost bits of the instruction word are sufficient to identify its format.
Format 1 instructions These are two-operand move, arithmetic, and comparison instructions. The first field of the word is a 4-bit operation code. The remaining four fields are a 2-bit addressing mode and 4-bit register number for the destination operand and a 2-bit addressing mode and 4-bit register number for the source operand. This format takes up 75% of available opcodes. 023456910111215OpcodeBTDDTSS MOV (move word) MOVB (move byte) A (add word) AB (add byte) S (subtract word) SB (subtract byte) C (compare word) CB (compare byte) SZC (set zeros corresponding word) SZCB (set zeros corresponding byte) SOC (set ones corresponding word) SOCB (set ones corresponding byte)
Format 2 instructions These operands are jump and CRU bit-manipulation instructions. The first field of the word is an 8-bit operation code. The second field is an 8-bit PC-relative offset to where to go for jump instructions or the relative offset for CRU bit addressing. 07815OpcodeOffset JMP (jump unconditionally) JLT (jump if less than zero) JLE (jump if less than or equal to zero) JEQ (jump if zero) JHE (jump if logically greater than or equal to zero) JGT (jump if greater than zero) JNE (jump if not equal zero) JNC (jump if carry clear) JOC (jump if carry set) JNO (jump if overflow clear) JOP (jump if odd parity - only relevant after byte operations) JL (jump if logically less than zero) JH (jump if logically greater than zero) SBO (set CRU bit to one) SBZ (set CRU bit to zero) TB (test CRU bit)
Format 3 instructions The first field of the word is a 6-bit operation code. The second field is a 4-bit destination register number, and the third and fourth fields are a 2-bit addressing mode and 4-bit register number. 056910111215OpcodeDTSS COC (compare ones corresponding) CZC (compare zeros corresponding) XOR (exclusive or)
Format 4 instructions