The Pentium (also referred to as the i586 or P5 Pentium) is a microprocessor introduced by Intel on March 22, 1993. It is the first CPU using the Pentium brand... Considered the fifth generation in the x86 (8086) compatible line of processors,I.e. 8086/88, 186/286, 386, 486, P5. succeeding the i486 as the series flagship under the Intel brand, its implementation and microarchitecture was internally called P5.
Like the Intel i486, the Pentium is instruction set compatible with the 32-bit i386. It uses a very similar microarchitecture to the i486, but was extended enough to implement a dual integer pipeline design, as well as a more advanced floating-point unit (FPU) that was noted to be ten times faster than its predecessor.
The Pentium was succeeded at the workstation and server markets by the P6-based Pentium Pro in November 1995. In January 1997, the Pentium MMXOfficially known as Pentium with MMX Technology. was released, complementing the same basic microarchitecture of the original Pentium with the MMX instruction set, larger caches, and some other enhancements. It was succeeded at the top range by the Pentium II brand, while production of the P5 Pentium processors continued as low-end series until July 1999, when it was replaced by the Celeron processor, which had also replaced the 486 brand.
Overview The P5 Pentium is the first superscalar x86 processor, meaning that it was often able to execute two instructions at the same time.Rant, Jon, "Pentium Processor: Previewing Desktop Computing's Next Step", Intel Corporation, Microcomputer Solutions, March/April 1993, p. 1. Some techniques used to implement this were based on the earlier superscalar Intel i960 CA (1989), while other details were invented exclusively for the P5 design. Large parts were also copied from the i386 or i486, especially the strategies used to cope with the complicated x86 encodings in a pipelined fashion.As compared to a simple RISC processor like the i960. Just like the i486, the Pentium used both an optimized microcode system and RISC-like techniques, depending on the particular instruction, or part of instruction. The dual integer pipeline design is something that had been argued being impossible to implement for a CISC instruction set, by certain academics and RISC competitors.
Other central features include a redesigned and significantly faster floating-point unit, a wide 64-bit burst-mode data bus (external as well as internal), separate code and data caches, and many other techniques and features to enhance performance. It contains 256-bit internal data buses and write-back caches.Rant, Jon, "Pentium Processor: Previewing Desktop Computing's Next Step", Intel Corporation, Microcomputer Solutions, March/April 1993, p. 1. It does contain System Management Mode that has been implemented since the Intel's SL architecture.Hodson, Gerri, "Anatomy of Intel's Pentium Processor", Intel Corporation, Solutions, May/June 1993, Page 9.
The 66 MHz Pentium processor operates at 112 V1.1 Dhrystone MIPS and has SPECint92 rating of 64.5, a SPECfp92 rating of 56.9 and an iCOMP index rating of 567. The performance difference between 60- and 66-MHz version is about 10%.Rant, Jon, "Pentium Processor: Previewing Desktop Computing's Next Step", Intel Corporation, Microcomputer Solutions, March/April 1993, p. 1.
The P5 also has better support for multiprocessing compared to the i486 and is the first x86 CPU with hardware support for it, similar to IBM mainframe computers. Intel worked with IBM to define this ability and also designed it into the P5 microarchitecture. This ability was absent in prior x86 generations and x86 processors from competitors.
In order to employ the dual pipelines at their full potential, certain compilers were optimized to better exploit instruction-level parallelism, although not all applications would substantially gain from being recompiled. The faster FPU always enhanced floating-point performance significantly though, compared to the i486 or i387. Intel spent resources working with development tool vendors, independent software vendors and operating system (OS) companies to optimize their products.
Competitors included the superscalar PowerPC 601 (1993), SuperSPARC (1992), DEC Alpha 21064 (1992), AMD 29050 (1990), Motorola MC88110 (1991) and Motorola 68060 (1994), most of which also used a superscalar in-order dual instruction pipeline configuration, and the non-superscalar Motorola 68040 (1990) and MIPS R4000 (1991).
Etymology
The name "Pentium" is originally derived from the Greek word pente (), meaning "five", a reference to the prior numeric naming convention of Intel's 80x86 processors (8086–80486), with the Latin ending , since the processor would otherwise have been named 80586 using that convention.
Development
The P5 microarchitecture was designed by the same Santa Clara team which designed the 386 and 486. Design work started in June 1989; the team decided to use a superscalar RISC architecture which would be a convergence of RISC and CISC technology,House, Dave, "Putting the RISC vs. CISC Debate to Rest", Intel Corporation, Microcomputer Solutions, November/December 1991, p. 18 with on-chip cache, floating-point, and branch prediction.Ivey, Mark, "Building the Pentium Processor" Intel Corporation, Solutions, May/June 1993, page 4 Vinod Dham then the Vice President of the Microprocessor Product Group and General Manager of Microprocessor Division 5/7 had the concept using this RISC technology into the existing x86 architecture that could compete from the other market.Ivey, Mark, "Building the Pentium Processor" Intel Corporation, Solutions, May/June 1993, page 4 Their performance target could boost FPU by three times and five time over the existing Intel486 CPU.Ivey, Mark, "Building the Pentium Processor" Intel Corporation, Solutions, May/June 1993, page 4 The preliminary design was first successfully simulated in 1990, followed by the laying-out of the design. By this time, the team had several dozen engineers. It took some 100 million clock cycles of pre-silicon verification test which includes major operating systems and many application were booted and running. They had to use the Quickturn Systems Inc. software to run pre-silicon simulation program which was 30,000 times quicker than the previous technique method available.Chen, Allan, Editor; Hodson Gerri, Associate Editor, "Intelperspectives: Intel's Newsletter for MIS Professionals, Volume 2, Number 1", Intel Corporation, Microcomputer Solutions, January/February 1993. p. 11 By late 1990, they found that the planned feature could not fit into the die, they had to redesign the circuit feature that would slim down in order to fit what the intended design in place without sacrificing the performance. In spring of 1991, the die went another slimming procedure until Dham was happy with the size and its feature without affecting the performance. A group of engineers ran hundreds of tests to validate the designed features and ran 5000 different variables to validate its design. Out of the 14 circuit boards in collection and cables, they only found few bugs using every operating system they have it on hand including in development were used.Ivey, Mark, "Building the Pentium Processor" Intel Corporation, Solutions, May/June 1993, page 4 By February 1992, the design was taped out in process which was completed by April 1992, at which point beta-testing began.Ivey, Mark, "Building the Pentium Processor" Intel Corporation, Solutions, May/June 1993, page 4 The next few months the design was sent to the Intel's Mask Operation which it translate to mask layout for the Oregon's Fab 5 to be processed.Ivey, Mark, "Building the Pentium Processor" Intel Corporation, Solutions, May/June 1993, page 4 By mid-1992, the P5 team had 200 engineers. Intel at first planned to demonstrate the P5 in June 1992 at the trade show PC Expo, and to formally announce the processor in September 1992, but design problems forced the demo to be cancelled, and the official introduction of the chip was delayed until the spring of 1993. The first computer systems featuring the Pentium appeared in the summer of 1993, the first being Advanced Logic Research and their Evolution V workstation, released in the first week of July 1993.
John H. Crawford, chief architect of the original 386, co-managed the design of the P5, along with Donald Alpert, who managed the architectural team. Dror Avnon managed the design of the FPU. Vinod K. Dham was general manager of the P5 group.
Intel's Larrabee multicore architecture project uses a processor core derived from a P5 core (P54C), augmented by multithreading, 64-bit instructions, and a 16-byte wide vector processing unit.§3 of Intel's low-powered Bonnell microarchitecture employed in early Atom processor cores also uses an in-order dual pipeline similar to P5.
Intel used the Pentium name instead of 586, because in 1991, it had lost a trademark dispute over the "386" trademark, when a judge ruled that the number was generic. The company hired Lexicon Branding to come up with a new, non-numeric name.
Improvements over the i486 The P5 microarchitecture brings several important advances over the prior i486 architecture. Performance: Superscalar architecture – The Pentium has two datapaths (pipelines) that allow it to complete two instructions per clock cycle in many cases. The main pipe (U) can handle any instruction, while the other (V) can handle the most common simple instructions. The first instruction goes to the U pipeline, then the next instruction goes to the V pipeline. Both pipelines contain their own ALU, address generation circuitry and interface to the data cache.Hodson, Gerri, "Anatomy of Intel's Pentium Processor", Intel Corporation, Solutions, May/June 1993, Page 9 Some reduced instruction set computer (RISC) proponents had argued that the "complicated" x86 instruction set would probably never be implemented by a tightly pipelined microarchitecture, much less by a dual-pipeline design. The 486 and the Pentium demonstrated that this was indeed possible and feasible. 64-bit burst-mode external databus doubles the amount of information possible to read or write on each memory access and therefore allows the Pentium to load its code cache faster than the 80486; it also allows faster access and storage of 64-bit and 80-bit x87 FPU data. Internally, this CPU process the data at 32 bits wide. The external data to the memory is 64 bits wide which doubles the amount of data being transferred in one bus cycle. It includes several types of bus cycles which includes burst mode that loads 256-bit portions of data into its data cache in one bus cycle as well. This data width can transfer data up to 528 Mbytes per second from and to the memory. This rate has increased three-fold over its peak transfer rate of the 50-MHz Intel486 DX CPU.Hodson, Gerri, "Anatomy of Intel's Pentium Processor", Intel Corporation, Solutions, May/June 1993, Page 9