Timing closure in VLSI design and electronics engineering is the iterative design process of assuring all signals satisfy the timing requirements in a clocked synchronous circuit. The goal is to guarantee correct data transfer and reliable operation at the target clock frequency.
A synchronous circuit is composed of two types of primitive elements: combinatorial logic gates (NOT, AND, OR, NAND, NOR, XOR etc.), which process logic functions without memory, and sequential elements (flip-flops, latches, or registers), which can store data and are triggered by clock signals. Through timing closure, the circuit can be adjusted through layout improvement and netlist restructuring to modify path delays to make sure the outputs of logic gates arrive at the correct time relative to the clock signal.
integrated circuit (IC) designs have become increasingly complicated, with modern chips containing billions of transistors and highly interconnected logic. Every path in the design must satisfy its timing constraints, or the design may suffer from functional faults, unpredictable consequences, or system-level failure.
Timing closure is not a simple final validation step, but rather an iterative and comprehensive optimization process. It involves continual improvement of both the logical structure of the design and its physical implementation, such as adjusting gate's logical structure and refining placement and routing, in order to reliably meet all timing constraints across the entire chip.
Overview Clocked digital circuits must meet certain constraints to ensure proper operation. For example, the time delay along each path from the output of a D flip-flop, through combinatorial logic gates, then into the next D flip-flop input must satisfy (be less than) the time period between synchronizing clock pulses to the two flip flops. If this constraint is not met, so the delay through the elements is greater than the clock period, the circuit will not function correctly. Therefore, modifying the circuit to remove any timing failures is an important part of the logic design engineer's task.
The critical path refers to the longest path (in terms of delay) between any two sequential elements in a design. It defines the maximum delay of all register-to-register paths, and sets the minimum possible clock cycle time, which in turn limits the maximum speed of the chip. In simple design, the user can compute all possible path delays between elements manually, and adjust them until requirements are met. In modern designs with thousands to millions of elements this is impractical, and automation is required.
Timing constraints
In the process of IC design, the IC layout should satisfy geometric constraints and timing constraints. Geometric constraints refer to physical design regulations and rules imposed by the assembly process, such as correct cell alignment and minimum wire spacing. Timing constraints refer to the timing requirements that all signal paths should satisfy. Usually, before the output of the signal from flip-flop at the clock edge, the input signal should remain stable for a period called the setup time. After the electromagnetic signal reaches the next flip-flop at the clock edge, the signal should remain stable in the storage element for some time, which is called hold time. This yields two types of timing constraints:
Setup constraints (long-path constraints):
These constraints specify the time length before the clock edge of flip-flop where the data input signal should stay steady, so that the data has enough time to propagate through a logic path and reach the next flip-flop before the next clock edge. If the path delay is too long, it may violate setup time constraints and cause problematic data to be latched.
Hold constraints (short-path constraints):
These constraints specify the time length after the clock edge of flip-flop where the data input signal should stay stable. Violating a hold constraint can result in metastability or unwanted behaviors.
Hold time constraint:
Setup time constraint:
Where:
= combinational logic delay = clock period = setup time = hold time = clock-to-Q delay of the flip-flop
Timing closure iterative process Timing closure is a vital step that ensures that all signals reach their destinations by the required time, and the hold times are all satisfied, so the circuit works reliably. Designers start with the register-transfer level (RTL) abstraction and Verilog or VHDL code that describes the circuit. This is turned into a netlist, which is a collection of logic gates and connections, and used either to create the placement and routing of an IC, or to configure the FPGA hardware.
In both conventional ICs and FPGAs, both gate delays and wiring delays can vary considerably. If signals arrive too late, or too early, the design may fail timing. The timing constraints designers begin to define accurate and realistic timing constraints that reflect the system's performance goals, often in the Synopsys Design Constraint (SDC) format. These constraints may include clock period, input/output delays, multi-cycle paths, and setup/hold requirements. It's critical to analyze whether they are achievable, based on the logic architecture and path delays within the design. These constraints guide all downstream timing analysis and optimization processes.
Problems in timing closure and static timing analysis There are three main delays in the clocked synchronous circuit that are primarily considered:
Gate delay is the length of time it takes for a change in a gate's input to propagate to the output. It's often calculated as the time between a change at the input and the resulting change at the output.
Wire delay is also known as interconnect delay, meaning the time that takes for a data signal to propagate through metal wires (interconnect) between circuit element in a synchronous circuit. The delay is mostly caused by the resistance and capacitance of the wire.
Clock skew is the difference in arrival time of the same sourced clock signal at different parts of a synchronous circuit. When the clock signal propagates from its source, such as oscillator or clock generator, through many different paths in the circuit, the signal experience propagation delay, which caused the clock skew. In the graph below, the clock skew between points i and j is on a chip: While position i and j can vary. The diagram illustrates the concept of clock skew, which refers to the difference in clock arrival times at different flip-flops on a chip. Ideally, all clock signals should reach their destinations simultaneously; however, due to variations in routing, load, and physical placement, this is rarely achieved.
After logic synthesis and constraints analysis, the design undergoes static timing analysis (STA), a process explicitly designed to evaluate whether the circuit meets its defined timing constraints. These tools (such as Cadence Tempus, Synopsys PrimeTime, and Intel Timing Analyzer) can evaluate all timing paths in the design without requiring simulation, making them ideal for scalable and exhaustive analysis. In STA, the combinational circuit can represent as directed acyclic graph (DAG) where nodes represent the gates and links represent the interconnect. Both are annotated with their corresponding delays. Typically initially the clock skew is assumed to be negligible. This will be re-visited after place, route, and clock tree synthesis.
During this process, the STA engine computes:
Path delays: Total delay from one register to another through combinational logic. Slack: The difference between required arrival time and actual arrival time. Critical paths: The longest paths with the smallest (or zero) slack. Violations: Paths with negative slack, meaning they fail to meet timing.
Especially for slack, STA supposes the worst-case scenario where every gate transitions, and computes the slack for each node.
Where:
RAT = required arrival time AAT = actual arrival time
RAT is the required arrival time, meaning the latest time can transit in the required timing. AAT is the actual arrival time, meaning the latest actual transition time, and is defined at the output of every node. Negative slack at any input means the circuit doesn't meet timing, while positive slack at all inputs means the circuit meets timing.
Physical design Once the STA reports are generated, engineers can utilize timing optimization techniques, or design automation tools, to examine them to identify the critical or failing paths that need attention. They also optimize the physical layout by adjusting placement and routing. This loop repeats until all timing constraints are met.
Through logic synthesis and initial timing optimization, the physical layout of the chip should be mapped. Through placement, clock tree synthesis, and routing of these key steps, the physical designs are altered so that the timing behaviors can change significantly, and therefore reduce the path delays and enhance the timing in circuit.
1. Placement The EDA tool assigns physical locations to each standard cell (logic gates, flip-flops, etc.) on the IC. Placement can reduce path delays by placing interconnected cells close to each other. Wiring is only estimated at this point.
2. Clock tree synthesis (CTS) A balanced clock distribution network is built to deliver the clock signal to all sequential elements (flip-flops) evenly and synchronously. The CTS tries to minimize clock skew (difference in arrival time of the clock signal at different points) while controlling the clock latency (the delivery time of the clock signal to all sequential elements). It also tries to satisfy the maximum transition time and the maximum allowed capacitance to ensure the clock network meets design constraints. The clock skew affects hold and setup times. The clock skew is usually composed of local clock skew and global clock skew.
Commonly there are three types of CTS:
2.1.Single point CTS
A single point clock tree starts off from a single clock source and delivers the clock signal to all sequential elements in a tree structure. This method is easy to implement and is appropriate for low-frequency or multi-clock designs. Nevertheless, it will be unsuitable for high-frequency or large-scale designs because path asymmetry can lead to larger clock skew.
2.2.Clock mesh
A clock mesh dispatches the clock signal through a grid-like structure, providing enhanced clock balance and lesser skew, which is good for high-frequency designs. However, constructing a clock mesh means higher power and area overhead, and the design complexity will be increased.
2.3.Multi-source CTS
A multi-source clock tree integrates the advantages of single-point trees and clock meshes. The design is partitioned into multiple components, each with its own local clock source. This clock tree achieves low skew while reducing power and area consumption, making it well-suited for large-scale designs.
3. Routing
After placement and clock tree synthesis, the design automation tool creates wires to physically connect cells. The physical routing introduces actual parasitic resistance and capacitance effects, which can affect signal delay. Incorporating these parasitics enables more precise timing analysis. The routing can help with timing closure by giving the nets with the least slack the most direct (and hence fastest) routes.
Timing optimization techniques One common way to improve the circuit performance is to use timing optimization techniques, such as inserting a register in between the combinational path of the critical path. This might improve the performance but increases the total latency (maximum number of registers from input to output path) of the circuit.