Digital Equipment Corporation (DEC)'s PDP-10, later marketed as the DECsystem-10, is a mainframe computer family: "It was large—even DEC's own literature called [the PDP-10] a mainframe." manufactured from 1966, delivered from December 1967, and discontinued in 1983. 1970s models and beyond were marketed under the DECsystem-10 name, especially as the TOPS-10 operating system became widely used.
The PDP-10's architecture is almost identical to that of DEC's earlier PDP-6, sharing the same 36-bit word length and slightly extending the instruction set. The main difference was a greatly improved hardware implementation. Some aspects of the instruction set are unusual, most notably the byte instructions, which operate on bit fields of any size from 1 to 36 bits inclusive, according to the general definition of a byte as a contiguous sequence of a fixed number of bits, as opposed to its modern definition of "eight bits".
The PDP-10 was found in many university computing facilities and research labs during the 1970s, the most notable being Harvard University's Aiken Computation Laboratory, MIT's AI Lab and Project MAC, Stanford's SAIL, Computer Center Corporation (CCC), ETH (ZIR), and Carnegie Mellon University. Its main operating systems, TOPS-10 and TENEX, and to a lesser extent ITS at a small number of influential locations, were used to build out the early ARPANET. The 36-bit words were especially well suited to Lisp at the time, because split in two parts 18 bits each to be used as pointers, it could address 256K objects instead of 64K on an equivalent 32-bit machine. For these reasons, the PDP-10 looms large in early hacker folklore.
Projects to extend the PDP-10 line were eclipsed by the success of DEC's unrelated VAX superminicomputer, and the cancellation of the PDP-10 line was announced in 1983. According to reports, DEC sold "about 1500 DECsystem-10s by the end of 1980".
Models and technical evolution
The original PDP-10 processor is the KA10, introduced in 1968. It uses discrete transistors packaged in DEC's Flip-Chip technology, with backplanes wire-wrapped via a semi-automated manufacturing process. Its cycle time is 1 μs and its add time 2.1 μs.Digital Equipment Corporation, The digital small computer handbook, p. 376. In 1973, the KA10 was replaced by the KI10, which uses transistor–transistor logic (TTL) SSI. This was joined in 1975 by the faster KL10 which is built from emitter-coupled logic (ECL), microprogrammed, and has cache memory. The KL10's performance was about 1 megaflops using 36-bit floating-point numbers on matrix row reduction. It was slightly faster than the newer VAX-11/750, although more limited in memory.
A smaller, less expensive model, the KS10, was introduced in 1978, using TTL and Am2901 bit-slice components and including the PDP-11 Unibus to connect peripherals. The KS10 was marketed as the DECSYSTEM-2020, part of the DECSYSTEM-20 range; it was DEC's entry in the distributed processing arena, and it was introduced as "the world's lowest cost mainframe computer system".
KA10 The KA10 has a maximum main memory capacity (both virtual and physical) of 256 kilowords (equivalent to 1152 kilobytes); the minimum main memory required is 16 kilowords. As supplied by DEC, it did not include paging hardware; memory management consists of two sets of protection and relocation registers, called base and bounds registers. This allows each half of a user's address space to be limited to a set section of main memory, designated by the base physical address and size. This allows the model of separate read-only shareable code segment (normally the high segment) and read-write data/stack segment (normally the low segment) used by TOPS-10 and later adopted by Unix. Some KA10 machines, first at MIT, and later at Bolt, Beranek and Newman (BBN), were modified to add virtual memory and support for demand paging, and more physical memory.
The KA10 weighs about .
The 10/50 was the top-of-the-line uniprocessor KA machine at the time when the PA1050 software package was introduced. Two other KA10 models were the uniprocessor 10/40, and the dual-processor 10/55.
KI10 The KI10 introduced support for paged memory management and for a larger physical address space of 4 megawords. KI10 models include 1060, 1070 and 1077, the latter incorporating two CPUs.
KL10
The original KL10 PDP-10 (also marketed as DECsystem-10) models (1080, 1088, etc.) use the original PDP-10 memory bus, with external memory modules. Module in this context meant a cabinet, dimensions roughly with a capacity of 32 to 256 kWords of magnetic-core memory. The processors used in the DECSYSTEM-20 (2040, 2050, 2060, 2065), commonly but incorrectly called "KL20", use internal memory, mounted in the same cabinet as the CPU. The 10xx models also have different packaging; they come in the original tall PDP-10 cabinets, rather than the short ones used later on for the DECSYSTEM-20. The differences between the 10xx and 20xx models were primarily which operating system they ran, either TOPS-10 or TOPS-20. Apart from that, differences are more cosmetic than real; some 10xx systems have "20-style" internal memory and I/O, and some 20xx systems have "10-style" external memory and an I/O bus. In particular, all ARPAnet TOPS-20 systems had an I/O bus because the AN20 IMP interface was an I/O bus device. Both could run either TOPS-10 or TOPS-20 microcode and thus the corresponding operating system.
Model B The later Model B version of the 2060 processors removes the 256 kiloword limit on the virtual address space by supporting up to 32 "sections" of up to 256 kilowords each, along with substantial changes to the instruction set. The two versions are effectively different CPUs. The first operating system that takes advantage of the Model B's capabilities is TOPS-20 release 3, and user mode extended addressing is offered in TOPS-20 release 4. TOPS-20 versions after release 4.1 only run on a Model B.
TOPS-10 versions 7.02 and 7.03 also use extended addressing when run on a 1090 (or 1091) Model B processor running TOPS-20 microcode.
MCA25 The final upgrade to the KL10 was the MCA25 upgrade of a 2060 to 2065 (or a 1091 to 1095), which gave some performance increases for programs running in multiple sections.
Massbus The I/O architecture of the 20xx series KL machines is based on a DEC bus design called the Massbus. While many attributed the success of the PDP-11 to DEC's decision to make the PDP-11 Unibus an open architecture, DEC reverted to prior philosophy with the KL, making Massbus both unique and proprietary. Consequently, there were no aftermarket peripheral manufacturers who made devices for the Massbus, and DEC chose to price their own Massbus devices, notably the RP06 disk drive, at a substantial premium above comparable IBM-compatible devices. CompuServe for one, designed its own alternative disk controller that could operate on the Massbus, but connect to IBM style 3330 disk subsystems.
Front-end processors
The KL class machines have a PDP-11/40 front-end processor for system start-up and monitoring. The PDP-11 is booted from a dual-ported RP06 disk drive (or alternatively from an 8" floppy disk drive or DECtape), and then commands can be given to the PDP-11 to start the main processor, which is typically booted from the same RP06 disk drive as the PDP-11. The PDP-11 performs watchdog functions once the main processor is running.
Communication with IBM mainframes, including Remote Job Entry (RJE), was accomplished via a DN61 or DN-64 front-end processor, using a PDP-11/40 or PDP-11/34a.
KS10
The KS10 is a lower-cost PDP-10 built using AMD 2901 bit-slice chips, with an Intel 8080A microprocessor as a control processor. The KS10 design was crippled to be a Model A, even though most of the necessary data paths needed to support the Model B architecture are present. This was no doubt intended to segment the market, but it greatly shortened the KS10's product life.
The KS system uses a similar boot procedure to the KL10. The 8080 control processor loads the microcode from an RM03, RM80, or RP06 disk or magnetic tape and then starts the main processor. The 8080 switches modes after the operating system boots and controls the console and remote diagnostic serial ports.
Magnetic tape drives Two models of tape drives were supported by the TM10 Magnetic Tape Control subsystem: TU20 Magnetic Tape Transport – 45 ips (inches per second) TU30 Magnetic Tape Transport – 75 ips (inches per second) TU45 Magnetic Tape Transport – 75 ips (inches per second) A mix of up to eight of these could be supported, using 7-track or 9-track devices. The TU20 and TU30 each came in A (9-track) and B (7-track) versions, and all of the aforementioned tape drives could read/write from/to 200 BPI, 556 BPI and 800 BPI IBM-compatible tapes.
The TM10 Magtape controller was available in two submodels: TM10A did cycle-stealing to/from PDP-10 memory using the KA10 Arithmetic Processor TM10B accessed PDP-10 memory using a DF10 Data Channel, without "cycle stealing" from the KA10 Arithmetic Processor
Instruction set architecture From the first PDP-6s to the KL-10 and KS-10, the user-mode instruction set architecture is largely the same. This section covers that architecture. The only major change to the architecture is the addition of multi-section extended addressing in the KL-10; extended addressing, which changes the process of generating the effective address of an instruction, is briefly discussed at the end. Generally, the system has 36-bit words and instructions, and 18-bit addresses.
Registers + DEC PDP-10 registers 00 . . . 17 18 . . . 35 (bit position) General registers AC0 Register 0 AC1 Register 1 AC2 Register 2 AC3 Register 3 AC4 Register 4 AC5 Register 5 AC6 Register 6 AC7 Register 7 AC10 Register 8 AC11 Register 9 AC12 Register 10 AC13 Register 11 AC14 Register 12 AC15 Register 13 AC16 Register 14 AC17 Register 15 Program counter and status flags Program Flags 00000 PC Program Counter Note that the bit numbering order is different from some other DEC processors, and many newer processors.
There are 16 general-purpose, 36-bit registers. The right half of these registers (other than register 0) may be used for indexing. A few instructions operate on pairs of registers. The "PC Word" register is split in half; the right 18 bits contains the program counter and the left 13 bits contains the processor status flags, with five zeros between the two sections. The condition register bits, which record the results of arithmetic operations (e.g. overflow), can be accessed by only a few instructions.
In the original KA-10 systems, these registers are simply the first 16 words of main memory. The "fast registers" hardware option implements them as registers in the CPU, still addressable as the first 16 words of memory. Some software takes advantage of this by using the registers as an instruction cache by loading code into the registers and then jumping to the appropriate address; this is used, for example, in Maclisp to implement one version of the garbage collector. Later models all have registers in the CPU.
Supervisor mode There are two operational modes, supervisor and user mode. Besides the difference in memory referencing described above, supervisor-mode programs can execute input/output operations.
Communication from user-mode to supervisor-mode is done through Unimplemented User Operations (UUOs): instructions which are not defined by the hardware, and are trapped by the supervisor. This mechanism is also used to emulate operations which may not have hardware implementations in cheaper models.
Data types