The MSP430 is a mixed-signal microcontroller family from Texas Instruments, first introduced on 14 February 1992. Built around a CPU, the MSP430 was designed for low power consumption,MSP430 will run on grapes – video on YouTube embedded applications and low cost.
Features
The fundamental feature of the MSP430 is low power consumption. The first MSP430s (MSP430C3xx) had a consumption around 400 uA/MHz and less than 2 uA in low-power mode with active basic timer and LCD driver. The more recent MSPs (MSP430FR5xx) have active mode consumption around 100-120 uA/MHz and 500 nA in low-power mode with active RTC. The consumption of the CPU itself is less than 32 uA/MHz. The MSP430FR series, which use FRAM instead of a flash, also allow fast writing to a non-volatile memory without additional power requirements.
The MSP430s use up to seven different low-power modes. The wake-up times differ on the mode and MSP430 generation. The fastest MSP430-family processors have wake-up times under 1 microsecond.
The MSP430s can run up to 25 MHz, while register-to-register operations take 1 cycle per instruction. The MSP430 family has more than 550 types, not counted package variants. There are microcontrollers with 0.5–512 KB flash or 0.5–256 KB FRAM and up to 66 KB RAM.
The device comes in a variety of generations featuring the usual peripherals:
Internal oscillator, Timer including pulse-width modulation (PWM), Watchdog timer, USART, Serial Peripheral Interface (SPI) bus, Inter-Integrated Circuit (I²C), Analog-to-digital converter (ADC) options: 10/12/14-bit successive-approximation ADC 16/24-bit delta–sigma ADC internal analog comparator with digital timers Can measure resistor-capacitor slope charging time Brownout reset circuitry.
Some less usual peripheral options include on-chip operational amplifiers (op-amp) for signal conditioning, 12-bit digital-to-analog converter (DAC), liquid crystal display (LCD) driver, hardware multiplier, USB, and direct memory access (DMA) for ADC results. Apart from some older erasable programmable read-only memory (EPROM, such as MSP430E3xx) and high volume mask ROM (MSP430Cxxx) versions, all of the devices are in-system programming enabled via Joint Test Action Group (JTAG), full four-wire or Spy-Bi-Wire), a built in bootstrapping loader (BSL) using UART such as RS-232, or USB on devices with USB support. No BSL is included in F20xx, G2xx0, G2xx1, G2xx2, or I20xx family devices.
Memory limitations There are, however, limits that preclude its use in more complex embedded systems. The MSP430 does not have an external memory bus, so it is limited to on-chip memory, up to 512 KB flash memory and 66 KB random-access memory (RAM), which may be too small for applications needing large buffers or data tables. Also, although it has a DMA controller, it is very difficult to use it to move data off the chip due to a lack of a DMA output strobe.D. Peters, D. Raskovic, and D. Thorsen, "An Energy Efficient Parallel Embedded System for Small Satellite Applications", ISAST Transactions on Computers and Intelligent Systems, vol. 1(2), 2009
MSP430 CPU + Texas Instruments MSP430 registers 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position) PC/R0 Program Counter SP/R1 Stack Pointer reserved V power I N Z C Status Register CG2/R3 Constant Generator R4 GP Register 4 R5 GP Register 5 R6 GP Register 6 R7 GP Register 7 R8 GP Register 8 R9 GP Register 9 R10 GP Register 10 R11 GP Register 11 R12 GP Register 12 R13 GP Register 13 R14 GP Register 14 R15 GP Register 15 Architecture The MSP430 CPU uses a von Neumann architecture, with a single address space for instructions and data. Memory is byte-addressed, and pairs of bytes are combined little-endian to make 16-bit words.
The processor contains 16 16-bit registers, of which four are dedicated to special purposes: R0 is the program counter, R1 is the stack pointer, R2 is the status register, and R3 is a "constant generator" which reads as zero and ignores writes. Added address mode encodings using R3 and R2 allow a total of six commonly used constant values (0, 1, 2, 4, 8 and −1) without needing an immediate operand word. R4 through R15 are available for general use.
The instruction set is very simple: 27 instructions exist in three categories. Most instructions occur in .B (8-bit byte) and .W (16-bit word) suffixed versions, depending on the value of a B/W bit: the bit is set to 1 for 8-bit and 0 for 16-bit. A missing suffix is equivalent to .W. Byte operations to memory affect only the addressed byte, while byte operations to registers clear the most significant byte.
The 10-bit signed jump offset is stored as a word displacement. The offset is doubled before being added to the PC. 16-bit jumps can be implemented with a MOV or ADD instruction
Instruction set +MSP430 instruction set 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Instruction 0 0 0 1 0 0 opcode B/W As register Single-operand arithmetic 0 0 0 1 0 0 0 0 0 B/W As register RRC Rotate right (1 bit) through carry 0 0 0 1 0 0 0 0 1 0 As register SWPB Swap bytes 0 0 0 1 0 0 0 1 0 B/W As register RRA Rotate right (1 bit) arithmetic 0 0 0 1 0 0 0 1 1 0 As register SXT Sign extend byte to word 0 0 0 1 0 0 1 0 0 B/W As register PUSH Push value onto stack 0 0 0 1 0 0 1 0 1 0 As register CALL Subroutine call; push PC and move source to PC 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 RETI Return from interrupt; pop SR then pop PC 0 0 1 condition 10-bit signed offset Conditional jump; PC = PC + 2×offset + 2 0 0 1 0 0 0 10-bit signed offset JNE/JNZ Jump if not equal/zero 0 0 1 0 0 1 10-bit signed offset JEQ/JZ Jump if equal/zero 0 0 1 0 1 0 10-bit signed offset JNC/JLO Jump if no carry/lower 0 0 1 0 1 1 10-bit signed offset JC/JHS Jump if carry/higher or same 0 0 1 1 0 0 10-bit signed offset JN Jump if negative 0 0 1 1 0 1 10-bit signed offset JGE Jump if greater or equal 0 0 1 1 1 0 10-bit signed offset JL Jump if less 0 0 1 1 1 1 10-bit signed offset JMP Jump (unconditionally) opcode source Ad B/W As destination Two-operand arithmetic 0 1 0 0 source Ad B/W As destination MOV Move source to destination 0 1 0 1 source Ad B/W As destination ADD Add source to destination 0 1 1 0 source Ad B/W As destination ADDC Add source and carry to destination 0 1 1 1 source Ad B/W As destination SUBC Subtract source from destination (with carry) 1 0 0 0 source Ad B/W As destination SUB Subtract source from destination 1 0 0 1 source Ad B/W As destination CMP Compare (pretend to subtract) source from destination 1 0 1 0 source Ad B/W As destination DADD Decimal add source to destination (with carry) 1 0 1 1 source Ad B/W As destination BIT Test bits of source AND destination 1 1 0 0 source Ad B/W As destination BIC Bit clear (dest &= ~src) 1 1 0 1 source Ad B/W As destination BIS Bit set (logical OR) 1 1 1 0 source Ad B/W As destination XOR Exclusive or source with destination 1 1 1 1 source Ad B/W As destination AND Logical AND source with destination (dest &= src) Instructions are 16 bits, followed by up to two 16-bit extension words. Addressing modes are specified by the 2-bit source addressing mode (As) and the 1-bit destination addressing mode (Ad) fields. Some special versions can be constructed using R0, and modes other than register direct using R2 (the status register) and R3 (the constant generator) are interpreted specially. As Ad is only 1-bit, it can specify only a subset of the addressing modes for As.
Indexed addressing modes add a 16-bit extension word to the instruction. If both source and destination are indexed, the source extension word comes first. x refers to the next extension word in the instruction stream in the table below.
+MSP430 addressing modes As Ad Register Syntax Description 00 0 n Rn Register direct. The operand is the contents of Rn. 01 1 n x(Rn) ||align=left| Indexed. The operand is in memory at address Rn+x. |- | 10 || — || n || @Rn Register indirect. The operand is in memory at the address held in Rn. 11 — n @Rn+ Indirect autoincrement. As above, then the register is incremented by 1 or 2. Addressing modes using R0 (PC) 01 1 0 (PC) ADDR Symbolic. Equivalent to x(PC). The operand is in memory at address PC+x. 11 — 0 (PC) #x Immediate. Equivalent to @PC+. The operand is the next word in the instruction stream. Addressing modes using R2 (SR) and R3 (CG), special-case decoding 01 1 2 (SR) &ADDR Absolute. The operand is in memory at address x. 10 — 2 (SR) #4 Constant. The operand is the constant 4. 11 — 2 (SR) #8 Constant. The operand is the constant 8. 00 — 3 (CG) #0 Constant. The operand is the constant 0. 01 — 3 (CG) #1 Constant. The operand is the constant 1. There is no index word. 10 — 3 (CG) #2 Constant. The operand is the constant 2. 11 — 3 (CG) #−1 Constant. The operand is the constant −1.
Instructions generally take 1 cycle per word fetched or stored, so instruction times range from 1 cycle for a simple register-register instruction to 6 cycles for an instruction with both source and destination indexed.
The MSP430X extension with 20-bit addressing adds added instructions that can require up to 10 clock cycles. Setting or clearing a peripheral bit takes two clocks. A jump, taken or not takes two clocks. With the 2xx series 2 MCLKs is 125 ns at 16 MHz.
Moves to the program counter are allowed and perform jumps. Return from subroutine, for example, is implemented as MOV @SP+,PC.
When R0 (PC) or R1 (SP) are used with the autoincrement addressing mode, they are always incremented by two. Other registers (R4 through R15) are incremented by the operand size, either 1 or 2 bytes.
The status register contains four arithmetic status bits, a global interrupt enable, and four bits that disable various clocks to enter low-power mode. When handling an interrupt, the processor saves the status register on the stack and clears the low-power bits. If the interrupt handler does not modify the saved status register, returning from the interrupt will then resume the original low-power mode.
Pseudo-operations Many added instructions are implemented as aliases for forms of the above. For example, there is no specific "return from subroutine" instruction, but it is implemented as MOV @SP+,PC. Emulated instructions are:
+ MSP430 Emulated instructions Emulated Actual Description ADC.x dst ADDC.x #0,dst Add carry to destination BR dst MOV dst,PC Branch to destination CLR.x dst MOV.x #0,dst Clear destination CLRC BIC #1,SR Clear carry bit CLRN BIC #4,SR Clear negative bit CLRZ BIC #2,SR Clear zero bit DADC.x dst DADD.x #0,dst Decimal add carry to destination DEC.x dst SUB.x #1,dst Decrement DECD.x dst SUB.x #2,dst Double decrement DINT BIC #8,SR Disable interrupts EINT BIS #8,SR Enable interrupts INC.x dst ADD.x #1,dst Increment INCD.x dst ADD.x #2,dst Double increment INV.x dst XOR.x #−1,dst Invert NOP MOV R3,R3 No operation POP dst MOV @SP+,dst Pop from stack RET MOV @SP+,PC Return from subroutine RLA.x dst ADD.x dst,dst Rotate left arithmetic (shift left 1 bit) RLC.x dst ADDC.x dst,dst Rotate left through carry SBC.x dst SUBC.x #0,dst Subtract borrow (1−carry) from destination SET.x dst MOV.x #-1,dst Set destination SETC BIS #1,SR Set carry bit SETN BIS #4,SR Set negative bit SETZ BIS #2,SR Set zero bit TST.x dst CMP.x #0,dst Test destination Note that the immediate constants −1 (0xffff), 0, 1, 2, 4 and 8 can be specified in a single-word instruction without needing a separate immediate operand.
MSP430X 20-bit extension The basic MSP430 cannot support more memory (ROM + RAM + peripherals) than its 64K address space. In order to support this, an extended form of the MSP430 uses 20-bit registers and a 20-bit address space, allowing up to 1 MB of memory. This uses the same instruction set as the basic form, but with two extensions: A limited number of 20-bit instructions for common operations, and A general prefix word mechanism that can extend any instruction to 20 bits.