X86 debug register

On the x86 architecture, a debug register is a register used by a processor for program debugging. There are six debug registers, named DR0...DR7, with DR4 and DR5 as obsolete synonyms for DR6 and DR7. The debug registers allow programmers to selectively enable various debug conditions associated with a set of four debug addresses. Two of these registers are used to control debug features. These registers are accessed by variants of the MOV instruction. A debug register may be either the source operand or destination operand. The debug registers are privileged resources; the MOV instructions that access them can only be executed at privilege level zero. An attempt to read or write the debug registers when executing at any other privilege level causes a general protection fault.

DR0 to DR3 Each of these registers contains the linear address associated with one of four breakpoint conditions. Each breakpoint condition is further defined by bits in DR7.

The debug address registers are effective whether or not paging is enabled. The addresses in these registers are linear addresses. If paging is enabled, the linear addresses are translated into physical addresses by the processor's paging mechanism. If paging is not enabled, these linear addresses are the same as physical addresses.

Note that when paging is enabled, different tasks may have different linear-to-physical address mappings. When this is the case, an address in a debug address register may be relevant to one task but not to another. For this reason the x86 has both global and local enable bits in DR7. These bits indicate whether a given debug address has a global (all tasks) or local (current task only) relevance.

DR6 - Debug status The debug status register permits the debugger to determine which debug conditions have occurred. When the processor detects an enabled debug exception, it will set the corresponding bits of this register before entering the debug exception handler.

Bits Abbreviation Description 0 B0 Breakpoint #0 Condition Detected 1 B1 Breakpoint #1 Condition Detected 2 B2 Breakpoint #2 Condition Detected 3 B3 Breakpoint #3 Condition Detected 10:4 11 BLD Cleared to 0 by the processor for Bus Lock Trap exceptions.Intel, Intel® 64 and IA-32 Architectures Software Developer’s Manual, order no. 325462-079, March 2023, Volume 3, chapter 18.2.3 and 18.3.1.6 on pages 3636 and 3643On processors that don't support Bus Lock Trap exceptions, bit 11 of DR6 is a read-only bit, acting in the same way as bits 10:4. 12 BK,SMMS (386/486 only) SMM or ICE mode entered (see also DR7, bit 12).Reserved and read as 0 on all later processors. 13 BD Debug Register Access Detected (see also DR7, bit 13). 14 BS Single-Step execution (enabled by EFLAGS.TF) 15 BT Task Switch breakpoint.Occurs when a task switch is done with a TSS that has the T (debug trap flag) bit set. 16 RTM (Processors with Intel TSX only)Cleared to 0 by the processor for debug exceptions inside RTM transactions, set to 1 for all debug exceptions outside transactions.On processors without TSX, bit 16 of DR6 is a read-only bit, acting in the same way as bits 31:17. 31:17 63:32

DR7 - Debug control The debug control register is used to selectively enable the four address breakpoint conditions, and to specify the type and size of each of the four breakpoints. There are two levels of enabling: the local (0,2,4,6) and global (1,3,5,7) levels. The local enable bits are automatically reset by the processor at every task switch to avoid unwanted breakpoint conditions in the new task. The global enable bits are not reset by a task switch; therefore, they can be used for conditions that are global to all tasks.

Bits Abbreviation Description 0 L0 Local enable for breakpoint #0. 1 G0 Global enable for breakpoint #0. 2 L1 Local enable for breakpoint #1. 3 G1 Global enable for breakpoint #1. 4 L2 Local enable for breakpoint #2. 5 G2 Global enable for breakpoint #2. 6 L3 Local enable for breakpoint #3. 7 G3 Global enable for breakpoint #3. 8 LE (386 only) Local Exact Breakpoint Enable. 9 GE (386 only) Global Exact Breakpoint Enable. 10 11 RTM (Processors with Intel TSX only)Enable advanced debugging of RTM transactions (only if DEBUGCTL bit 15 is also set)On other processors: reserved, read-only, read as 0 and should be written as 0. 12 IR,SMIE (386/486 processors only) Action on breakpoint match:0 = INT 1 (#DB exception, default)1 = Break to ICE/SMMOn other processors: Reserved, read-only, read as 0 and should be written as 0. 13 GD General Detect Enable. If set, will cause a debug exception on any attempt at accessing the DR0-DR7 registers. 15:14 17:16 R/W0 Breakpoint condition for breakpoint #0. 19:18 LEN0 Breakpoint length for breakpoint #0. 21:20 R/W1 Breakpoint condition for breakpoint #1. 23:22 LEN1 Breakpoint length for breakpoint #1. 25:24 R/W2 Breakpoint condition for breakpoint #2. 27:26 LEN2 Breakpoint length for breakpoint #2. 29:28 R/W3 Breakpoint condition for breakpoint #3. 31:30 LEN3 Breakpoint length for breakpoint #3. 32 DR0_PT_LOG Enable DR0/1/2/3 breakpoint match as a trigger input for PTTT (Processor Trace Trigger Tracing).Intel, Intel Architecture Instruction Set Extensions and Future Features, order no. 314933-053, Jun 2024, section 16.2.3, page 216. Archived on 28 Jul 2024.Read as 0 and must be written as all-0s on processors that don't support PTTT. 33 DR1_PT_LOG 34 DR2_PT_LOG 35 DR3_PT_LOG 63:36

DR4 and DR5 Not real registers. On processors that support the CR4.DE bit (Intel Pentium and later), their behaviour is controlled by CR4.DE: CR4.DE=0 : DR4 and DR5 alias to DR6 and DR7, respectively. CR4.DE=1 : accessing DR4/5 results in #UD (invalid opcode) exception. On processors without CR4.DE, the behaviour is officially undefined - usually, DR4/5 are aliased to DR6/7, but exceptions exist and have been used for CPU detection.Geoff Chappell, CPU Identification Before CPUID, 4 Mar 2023. Accessed on 6 Sep 2024. Archived on 3 Jun 2024.

X86 debug register

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